Cascaded Folding in Flash ADC

folding flash adc

In 1997 Dec. JSSCC, Aaron Buckwald raised cascaded folding concept in high speed ADC to reduce No. comparators.

The approach there is to first folding x3 and cascade another folding x3 after it.

I do not quite follow his paper. Since folding will induce large distortion and only zero crossing is used, further folding does not have a good reference voltage. How we give 2nd stage folding x3 a good reference?

folding adc explanation

I advise you to read

M.-J. Choe, B.-S. Song and K. Bacrania, “An 8-b 100-MSample/s CMOS pipelined folding ADC,” IEEE J. Solid-State Circuits, vol. 36, pp. 184-194, Feb. 2001.

in which there is a more or less clear explanation of cascaded folding. Anyway, I'll give a quick explanation:
-in a flash ADC the signal received by each comparator (output of the pre-amplifier) has only one zero-crossing for a certain code transition level of the ADC. So one latched comparator is needed to detect EACH code (<=> zero crossing).
-in a folding ADC the pre-amps are substituted by folding circuits, which have a transfer function with not one but several zero crossings. So now each comparator decides not one but several code transistion levels of the ADC -> LESS latched comparators are needed.
-when cascaded folding is used, the first stage is similar to what is found in a single-folding stage ADC (it receives input and reference voltages and generates the folding signals). However, the remaining stages - 2nd to the last - receive, as inputs, the outputs of the previous stage (so they don't receive reference voltages). Note that by cascading folding circuits NO new zero crossings are created - this operation simply joins more zero crossings in the same signal. In a ADC using a cascaded folding (and interpolation) architecture the zero crossings are only created in the 1st folding stage and by interpolation - the remaining folding stages do not create zero crossings.

Hope this helps.

Regards

flash adc folding

In 2001, Abidi published a paper of "A 6-b 1.3-Gsample/s A/D Converter in 0.35-um CMOS".

Only 6-bit resolution is required, however, Abidi and Michael Choi added 1pF as input sampling capacitor. The thermal noise due to KT/C is only about 2mV, which is much lower than LSB quantization noise. Why they put so much capacitance there and pay the cost for high power?

thanks,
Neo