EDA_hg81
Advanced Member level 2
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I have set timing constraint parameter,OFFSET OUT AFTER, with different values for the same net.
When I used FPGA editor to check, I found out the timing delay for the same net is same even I set OFFSET OUT AFTER with different values.
Do you think it is right?
Thanks.
When I used FPGA editor to check, I found out the timing delay for the same net is same even I set OFFSET OUT AFTER with different values.
Do you think it is right?
Thanks.