avt
Member level 5
set_input_delay
hi guys,
I have a funny porblem : I have a pair of lvds-receiver-pads - one for a clock signal, on for the data. The edges of the clock and the data are aligned within the buffer (with some additional skew detection cicuitry) - and the skew between the dges of the clock is smaller then 100ps - there is also some additional jitter (smaller then 100ps).
now I tried - just for a start - to synthesize just a flipflop for cpaturing the data. The funny thing is : when I use in the the dc-synthesis-script
"set_input_delay -clock clk 0.0 [all_inputs]"
and
"set_clock_latency 0 [get_clocks]"
- as it is obviously the case then I get the following timing violation :
min_delay/hold ('clk' group)
Required Actual
Endpoint Path Delay Path Delay Slack
-----------------------------------------------------------------
test_reg_1/out_reg/D 0.08 -0.09 f -0.17 (VIOLATED)
For the start I set the clock uncertainty to 0 - of course it shoul be at least 100ps due to jitter. But this would only even increase the problem ...
What I'm asking myself now - why the heck doesn't DC just infer some Buffer in the circuit or when will this happen ? (Do I have to do this by myself ?)
I'm puzzled - help me
hi guys,
I have a funny porblem : I have a pair of lvds-receiver-pads - one for a clock signal, on for the data. The edges of the clock and the data are aligned within the buffer (with some additional skew detection cicuitry) - and the skew between the dges of the clock is smaller then 100ps - there is also some additional jitter (smaller then 100ps).
now I tried - just for a start - to synthesize just a flipflop for cpaturing the data. The funny thing is : when I use in the the dc-synthesis-script
"set_input_delay -clock clk 0.0 [all_inputs]"
and
"set_clock_latency 0 [get_clocks]"
- as it is obviously the case then I get the following timing violation :
min_delay/hold ('clk' group)
Required Actual
Endpoint Path Delay Path Delay Slack
-----------------------------------------------------------------
test_reg_1/out_reg/D 0.08 -0.09 f -0.17 (VIOLATED)
For the start I set the clock uncertainty to 0 - of course it shoul be at least 100ps due to jitter. But this would only even increase the problem ...
What I'm asking myself now - why the heck doesn't DC just infer some Buffer in the circuit or when will this happen ? (Do I have to do this by myself ?)
I'm puzzled - help me