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PLL simple question??

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salem_eng1

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Hi All

I am working nowadays in system design of PLL frequency synthesizer for ZigBee.
From my search on the net and e-books I found some specs but not all I need so any one has this specs or have a simple tutorial for the ZigBee standard and its Physical layer please upload it


The specs I have :
-fc=2405+5*(k-11) MHz , k=11,12,........,26
-frequency range: 2.4GHz<fc<2.4835GHz
-Frequency tolerance: 40ppm
-Channel spacing=5MHz
-Channel B.W=2MHz
-Settling time=190usec
-Phase noise : -80dBc/Hz @ 3.5Mhz , -75 dBc/Hz @ 5Mhz , -105 dBc/Hz @ 10MHz

The specs I need
-Minimum SNR at the receiver input
-Minimum Rx power.
-Maximum Rx power
-spurs level at 5,10,15 MHz offset

My question is that I am not sure from the specs I have so any one can correct it to me if there is any mistake or tell me how to check it is right also I need the other specs I don't have can any one tell me how to get it
Thanx
 

salem_eng1 said:
Hi All

I am working nowadays in system design of PLL frequency synthesizer for ZigBee.
From my search on the net and e-books I found some specs but not all I need so any one has this specs or have a simple tutorial for the ZigBee standard and its Physical layer please upload it


The specs I have :
-fc=2405+5*(k-11) MHz , k=11,12,........,26
-frequency range: 2.4GHz<fc<2.4835GHz
-Frequency tolerance: 40ppm
-Channel spacing=5MHz
-Channel B.W=2MHz
-Settling time=190usec
-Phase noise : -80dBc/Hz @ 3.5Mhz , -75 dBc/Hz @ 5Mhz , -105 dBc/Hz @ 10MHz

The specs I need
-Minimum SNR at the receiver input
-Minimum Rx power.
-Maximum Rx power
-spurs level at 5,10,15 MHz offset

My question is that I am not sure from the specs I have so any one can correct it to me if there is any mistake or tell me how to check it is right also I need the other specs I don't have can any one tell me how to get it
Thanx
Click to expand...

hi

i think you can refer some papers for references.
good luck
jeff
 

    S

    salem_eng1

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Thanx jfyan

I tried to search some paper as you said but I found specs more than the minimum required
The problem is I am just a beginner on PLL design and I can't design the specs found in a paper.

I just want to Know the minimum required specs Like Phase noise. Not more than the minimum

Please any one can help he will be grateful

Thanx
regards
Salem
 

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