What are the details about level shifter and isolation cells

Hi ,
Can any body give details of the following ,,
1. level shifter ,
2.retention fliflop
3.Isolation cells,
4. Always on buffers.
5. power gates,footers,headers.

Hi I know the elementary infornmation about this so please give me more detail ............
if any body has good document regading this please upload here.


--
Regards,
Rakesh

Re: multi voltage flow

Level shifter is a special std-cells that is used to change voltage swing of signal when we have a signal across two voltage domain. There are two kind of level-shifter, shifter down and shifter up:
+ Shifter-down is used to down shift voltage swing of signal from high-voltage to low.
+ Shifter-up is used to down shift voltage swing of signal from low-voltage to high.

As you know, the std-cell have a particular voltage level (calls 'voltage domain') that is define as an operating condition (PVT) of that cell. A voltage domain has a particular operating condition that controls cell-delay and signal swing of cells into.

Nowaday, all EDA tools embeded the multi-voltage flow as a special flow for low-power design. ie: Magma, Synopsys, Cadence,... . Magma (www.magma-da.com) automatic detect all nets that need level-shifters, and automatic insert level-shifters into this nets.

I have some useful docs for low-power design. If you want to learn, please contact me:

Nguyen Phuc Vinh, vinh.camau@gmail.com,

Re: multi voltage flow

isolation cells r for completely turning off a particular power domain....

multi voltage flow

retention cells are used for low power designs .
They hold the output value,then that block can be switched off from power supply .when ever need ,the value will be loaded back from retention flop.

multi voltage flow

From these concepts, digital design is similar as analog more and more

multi voltage flow

My pence on Isolation cells :

Isolation cells are the cells that are used to isolate the power down block from the other parts of the design that are always-on.

A simple isolation cell can be an "And" gate - where one input to the and gate will the output of the power down block and another input can be the power down enable signal. In this case the power down enable signal will be active low. There by forcing the output of the and gate to logic 0. Thus when all the outputs of the power down logic are isolated using isoloation cell, when power down enable is activated (in this case active low) then all the output of the "and" isolation cell will be 0 .

Re: multi voltage flow

Isolation Cells:
Isolation cells can be connected to the input pins or output pins of the block which will be shut off.

Assume a scenario, that the top level design has block A , block B and block C. Also assume that the block C sits inside the Block B.

Block A - OFF, Block B - OFF and Block C - ON

The output pins of the block A needs to be connected to the isolation logic cells and it is not necessary to have the isolation cells for the input pins. The isolation cells for the block A will be placed at the top level and closer to the output pins of the block A

The input pins of the Block C needs to have the input isolation logic, while it is not necessary to have isolation cells at its output. Again only the input pins which get signals from Block B needs to have the isolation cells. These isolation cells are placed inside the block C.

Hope I have not confused the readers.

Again it is not necessary that every design which has a shut off block needs to have level shifters. The level shifters are used only if they operate at 2 different voltages at the blocks.

Shut off blocks also need to use switch cells. These switch cells have a control signal, which either turns on or off the block. These switch cells can be placed at the power supply net or to the ground net.

Hope this helps.

Re: multi voltage flow

hello
good discussion is going on here..
thanks
hardik

multi voltage flow

good solution by denmos , thatis great!

Re: multi voltage flow

Thank calm,

I have just tapped out a low power design (full chip). if you want to know how to perform multi-voltage design in EDA tool, please contact me!

I'm very please to help!

multi voltage flow

could somebody explain how to use scan chain and sram for retention

Re: multi voltage flow

Check out low power design guide

Re: multi voltage flow

vak said:

Isolation Cells:
The input pins of the Block C needs to have the input isolation logic, while it is not necessary to have isolation cells at its output. Again only the input pins which get signals from Block B needs to have the isolation cells. These isolation cells are placed inside the block C.
.

Click to expand...

Hi vak,

I know it's a very old discussion,but was just going through it and failed to understand something. Will you please care to explain,why will block C inputs require isolation? Since block resides within block b,which in turn is OFF, wouldn't block C goes off with it automatically?
Please correct if I'm wrong.

Thanks,
VD!

Re: Details about level shifter and isolation cells

as quoted "Block A - OFF, Block B - OFF and Block C - ON"; Block C is inside Block B, when Block B is off, unknown values become might propagate to Block C which we don't want to see. Isolation cells at the inputs of C are to prevent those unknown values being propagate downstream.

Re: Details about level shifter and isolation cells

Isolation cells are generally inserted in POWER ON domain than OFF domain, to prevent the don't cares coming into the ON block.

rakesh1234 said:

Hi ,
Can any body give details of the following ,,
1. level shifter ,
2.retention fliflop
3.Isolation cells,
4. Always on buffers.
5. power gates,footers,headers.

Hi I know the elementary infornmation about this so please give me more detail ............
if any body has good document regading this please upload here.


--
Regards,
Rakesh

Click to expand...

This link might answer your questions.
https://blogs.synopsys.com/magicblu...cial-cells-required-for-multi-voltage-design/