what about bjt size ?

emitter length bjt

i just think that ,
for mos we are change w/l for gain or ids current for designing .
what about bjt ?
what is the relation between the beta and its size (for bjt ) ?

bjt sizing

in bjt generally the emitter size is varied..... when it is varied the number of majority carriers emitted varies and hence varies the transistor parameters like beta... also here the doping can be varied to vary beta and other parameters....

about bjt

for layout design .
how i can varies the size of emitter in exact manner.
Any eqn ?

is bjt size

in bjt generally the emitter size is varied..... when it is varied the number of majority carriers emitted varies and hence varies the transistor parameters like beta...

Click to expand...

Manish, Are you dealing with a lateral bjt or a verticle bjt? The reason is Srinivasan's recommendation holds true only for a lateral bjt, eg. lateral pnp or npn devices. For a verticle bjt, "ideally" the beta should not vary with emitter dimensions, providing you are not operating in or near high-injection. For example, if you increase the emitter width, this will also increase the series base resistance which will cause beta to fall off at higher Vbe or Ic values, which is near or at the high-injection regime of the device.

There is another subtle effect due to the emitter/base profile, which differs from company/foundry to company/foundry. This causes beta to increase or decrease depending on the ratio of emitter bottom area to emitter periphery area. I won't waste people's time to go into details about this.

Normally under layout control you can vary the emitter size by increasing it in long thin strips interdigitated by base pickups to minimize base resistance effects but l don't think this would help you much in terms of β Since your base area and hence the base current is also increasing. This would although help you to get a higher current from your transistor. Higher current can also be delivered by connecting many transistors in parallel, though that may consume some more area. But this is why it may be preferable to stick with your unit transistor & Size it by creating multiples of it or use circuit schemes to enhance β. Since these units might be well characterized by the modeling people

Anand Srinivasan is right.. beta in bjt depends on the area of the emitter.. more the size more carriers are injected into collector. The BJT process optimizes the npn transistor at the cost of pnp. so the gain of npn will be around 100-150 while that of pnp will be around 30-50. For emitter size is concerned the foundry will fix a unit area.. for eg 1 unit area = 200 sq microns for npn and for pnp 1 unit area = 180 sq microns.. so if in the schematic there is an npn of unit size 2 .. they will start by drawing 2X200 = 400 sq microns emitter area.. square root of 400 = 20 .. emitter contains a square area of side 20 microns..

Thanks

krn, As I said before the area of the emitter is mainly dependent on a lateral type bjt. For a normal verticle bjt, beta is heavily dependent on the charge in the base (Qb). If you don't control your base charge, you will have a messed up bipolar process. In a typical flow the npn is a verticle device and the pnps are a lateral device. The base charge (Qb) is dependent on area of base region. The verticle npn's usually have a much narrower base width than the base width of a lateral pnp device. Therefore, the Qb is much different between the two devices, thus the lateral pnp has a much lower beta than the verticle npn bjt.

i agree with krashkeoloha.. also in lateral pnp the carriers move along the surface from the emitter to reach collector surrounding it.. due to discontinuities and surface effects some of the charges gets combined.. so the gain will be less.. but in vertical npn due to NBL and deep n+ regions reduces the collector resistance making most of the carriers to reach collector so more gain.. Also we have to increase the size of the emitter to prevent thermal runaway(large flow of current in a small area)..

Thanks