Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Floating nodes at CMOS usually refer to a transistor's gate that sees high impedance .The transistor's gate is of capacitive nature ,thus any charges can get trapped at this node .This may cause a transistor to be on will the designer thought that the transistor is off because no voltage is applied to the gate .This ambiguity (not being certain where the transistor is operating) is unwanted so the gate usually not left floating but os connected to a well defined voltage.
Any node through which we cannot figure out a path from VDD to ground can be considered as a floating node. There is no advantage of any such node but such nodes occur in a design due to many reasons. All such nodes need to be identified and should be tied to some logic inorder to avoid unexpected behavior of the design.
floating node can cause the unwanted voltage of any node which can cause the convergence issue. Therefore, problem in simulation that will say that no dc solution due to the convergence issue. Spectre dose it automatically by some method.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
