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A.Anand Srinivasan said:i agree with shiv_emf but i would like to add a point... in case 2 when the input voltage of terminal 3 starts increasing and at a point the output drops to zero and so the capacitor starts discharging through the resistor and hence the output would again become high quickly and this time period depends on the R and C values....
that would be true only when the input and output would be equal at a particular voltage and that level of matching is rare....i dont know influence of second NOR input over the first one , but if it is not interfering , for cmos logic , output voltage should half of power supply and logic ic should work in linear mode if button pressed for time more than multiple of R*C value .
polarity of C1 is wrong....Is it polarity of the c1 is correct?