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[HELP]layout of bandgap

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CISSE

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bandgap layout

I have some trouble in my first design project,bandgap.
In layout process,there are some problems:
First:pNP.I know the ratio 1:8.But how to draw them.Both the emitter and the base connect to the ground.
Second:resistor.How to draw them in precise value or ratio?
 

Hi there, For these ratio of transistor. The single trans should be covered with the remainng 8 on all sides abutted in square form.

Resistors in Bandgap should be very precise matching. see that both resistors have same w/l and try transitor matching patterns
like ABBA.
 
some of the ieee papers intro the layout
 

CISSE said:
I have some trouble in my first design project,bandgap.
In layout process,there are some problems:
First:pNP.I know the ratio 1:8.But how to draw them.Both the emitter and the base connect to the ground.
Second:resistor.How to draw them in precise value or ratio?
Click to expand...

Put quite a few dummies to match the bjts and resistors... Its very important!!
We, as designers, dont mind changing the schematic to include dummies :D

A good design will have the resistor's W/L ratios same.. so no need to worry too much on that.. just follow the matching rules in layout..

All the best!
 

thanks,rimser9
i mean in the n-well there is p diffusion and contact resistance because both the collection and the base connect to the ground.so the PNP cell can't be made as square but rectangle.is that OK?or i'm wrong.

Added after 1 minutes:

hi qutang
can you tell me these IEEE papers in detail？

Added after 20 minutes:

thanks，srieda
to tell the truth ，I dont‘t know the matching rules while i have read just some documents.this is my first project.can you tell me some books or experience?
oh,i also have a question in circuit design process.my PSRR just have -60DB.But my amp's PSRR have 90DB more.So how can i improve the PSRR?get the W/L of PMOS current source langer or take cascode structure?the first way has not much improvement.the second way it dosen't work because my power supply is 3.3V and the cascode pmos consume too much voltage.So the PNP can't work normally.is there any way alse?
 

Man. Yes we too use PNP. The outer diff i.e collector right.
so Place the single transistor in the center and then place the remaing 8 around this single trans such that the collectors abut each other. Use ur imagination to realize this. I cant send a snapshot.
 

collector is P-sub,so they are always together not abut.But the base(n-well)should be close and connected by metal.In the n-well there are two types of contact(the emitter and the base),so i have to use metal1 and metal2.Am i right?
 

Collector is Psub even then u have to abut all collectors. P-sub is different than P-diffusion. (doping diff).

Added after 3 minutes:

Use M3 and M2 to short all emitters. Collectors are p+ diffusion not P substrate.

Added after 3 minutes:

M1 to short base and collectors
 

oh，do you mean lateral PNP?
 

i consider it as vertical transistor，so the collector is P-sub.Can it be vertical transistor?Or which one is better?
 

Mostly evryonne uses vertical i.e lateral transistors as there will be discontinuties at the silicon surface which obstructs current flow.
 
thank you,rimser
what about the resistor.there are five,33K,33K,3.8K,8K,40K.the first three should have the precise ratio.so how to draw them?i decide to use p-diff resistor because the sheet resistor is 120.what about others,ploy?well?and i want to use the Interdigitate.the three resistors have the ratio 9:1:9,so i draw as follow:
DACCAACCAACCA|ACCAACCAACCAD
DACCAACBBCAACCA|ACCAACBBCAACCAD
DACCAACCAACCA|ACCAACCAACCAD
A=C=33K,B=3.8K,is that right?
and my bandgap layout occupy 110um*250um area. is that too large?
 
the bandgap circuits need the PN junctions to generate the positive and negative voltages.I have the layout of the vpnp and resistors.I wish the layout can help you.
 

the layout for vpnps and resistors
 

for the resistor,is that the p-diff?you use ABAB……i have three resistors,so,i use the structure that i've mentioned.and you use metal1 and metal2?what about the w/l.my choice is 1.5um/11um.is that ok?

Added after 4 minutes:

for PNP,what's LVT layer?
oh,great help!thanks,standup
 

Dear CISSE:

Please see the


I put BJT and R layout layout plant on it.
I think they are clear to know layout plant for these devices.

mpig
 

thanks,everyone.i have passed the verificafion.And i have learned many technology of LAYOUT.
thank you!
 

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