Urgent help with VHDL codes

hello all,
i am newbie here and i am currently working on an assignment.
for this assignment, i need to take in 10 bytes of data serially from RD232 into FPGA using VHDL codes and then display out on the 7-segment using MAX chip.besides, they can stored in SRAM.

i got no idea at all on how to start of this stuff. does anyone got the idea how they works? please tell me the basic concept and as well as explain in a block diagram or flow chart. further details how baud rate,frequency etc influent the program...

i need it urgently.

thank you!!

hi
you just first write code for transmitt data from serial interface i.e.RS232 & get synthesized it with synthesis tool maybe XST.for this you should know how RS232 works.
regards
shraddha

it is transmit? i thought should write a code on receiving?because i am taking data in from RS232...

thanks!

You will need to write your VHDL code to generate a decoder as you need to read the RS232 code and output a value on your 7 segment display.

Look at how a decoder works in VHDL (there are plenty of examples) in whoevers book you have as a reference. You will see that they take a known value coming into the device (you do know what data you will be recieving dont you) and they use a decoder to output whatever information they need.

Below is an example of a decoder. As you can see the data coming into the FIFO contains more bits than the data that is output. That is fine to do provided you follow proper naming conventions.

--- FIFO register selector decoder --- this is a dataflow construct that selects the FIFO register

with wrptr select
en <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;


E

for RS232 receiver you need to write code using state machine. U will have 2 states. First state will detect start bit and after that second state will take care of data with parity. U will go back to first state after recieving stop bit. for baud count u need to see what is ur operating frequency.

There was an reply by "Engr.Kamran Hameed" posted wrongly in report system. I copy it here (format it yourself).
----------------------------------------------

I am sending you UART verilog code which will be the main part of ur willing programming and this code will INSHALLAH help u a lot in completion of ur query module uart ( reset , txclk , ld_tx_data , tx_data , tx_enable , tx_out , tx_empty , rxclk , uld_rx_data , rx_data , rx_enable , rx_in , rx_empty ); // Port declarations input reset ; input txclk ; input ld_tx_data ; input [7:0] tx_data ; input tx_enable ; output tx_out ; output tx_empty ; input rxclk ; input uld_rx_data ; output [7:0] rx_data ; input rx_enable ; input rx_in ; output rx_empty ; // Internal Variables reg [7:0] tx_reg ; reg tx_empty ; reg tx_over_run ; reg [3:0] tx_cnt ; reg tx_out ; reg [7:0] rx_reg ; reg [7:0] rx_data ; reg [3:0] rx_sample_cnt ; reg [3:0] rx_cnt ; reg rx_frame_err ; reg rx_over_run ; reg rx_empty ; reg rx_d1 ; reg rx_d2 ; reg rx_busy ; // UART RX Logic always @ (posedge rxclk or posedge reset) if (reset) begin rx_reg <= 0; rx_data <= 0; rx_sample_cnt <= 0; rx_cnt <= 0; rx_frame_err <= 0; rx_over_run <= 0; rx_empty <= 1; rx_d1 <= 1; rx_d2 <= 1; rx_busy <= 0; end else begin // Synchronize the asynch signal rx_d1 <= rx_in; rx_d2 <= rx_d1; // Uload the rx data if (uld_rx_data) begin rx_data <= rx_reg; rx_empty <= 1; end // Receive data only when rx is enabled if (rx_enable) begin // Check if just received start of frame if ( ! rx_busy && ! rx_d2) begin rx_busy <= 1; rx_sample_cnt <= 1; rx_cnt <= 0; end // Start of frame detected, Proceed with rest of data if (rx_busy) begin rx_sample_cnt <= rx_sample_cnt + 1; // Logic to sample at middle of data if (rx_sample_cnt == 7) begin if ((rx_d2 == 1) && (rx_cnt == 0)) begin rx_busy <= 0; end else begin rx_cnt <= rx_cnt + 1; // Start storing the rx data if (rx_cnt > 0 && rx_cnt < 9) begin rx_reg[rx_cnt - 1] <= rx_d2; end if (rx_cnt == 9) begin rx_busy <= 0; // Check if End of frame received correctly if (rx_d2 == 0) begin rx_frame_err <= 1; end else begin rx_empty <= 0; rx_frame_err <= 0; // Check if last rx data was not unloaded, rx_over_run <= (rx_empty) ? 0 : 1; end end end end end end if ( ! rx_enable) begin rx_busy <= 0; end end // UART TX Logic always @ (posedge txclk or posedge reset) if (reset) begin tx_reg <= 0; tx_empty <= 1; tx_over_run <= 0; tx_out <= 1; tx_cnt <= 0; end else begin if (ld_tx_data) begin if ( ! tx_empty) begin tx_over_run <= 0; end else begin tx_reg <= tx_data; tx_empty <= 0; end end if (tx_enable && ! tx_empty) begin tx_cnt <= tx_cnt + 1; if (tx_cnt == 0) begin tx_out <= 0; end if (tx_cnt > 0 && tx_cnt < 9) begin tx_out <= tx_reg[tx_cnt -1]; end if (tx_cnt == 9) begin tx_out <= 1; tx_cnt <= 0; tx_empty <= 1; end end if ( ! tx_enable) begin tx_cnt <= 0; end end endmodule

pretty thanks for u all!! really appreciate for helping..!!^.^

now i am trying in some codes but faced some problem during compilation..does any of u willing to help me?