Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Explanation of the latch comparator operation

Status
Not open for further replies.
A

arc

Newbie level 6
Newbie level 6
Joined
Aug 30, 2006
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,380
hi...

can anyone give me the operation of latch comparator....???
also how to simulate the design in cadence analog environment....
Please help me out its urgent...

Thanks
 

Re: latch comparator

hi iam attaching some may be useful to u
 

Re: latch comparator

can anyone explain me... how we will decide the value of +Vref and -Vred in pipelined ADC circuit.....please find attachment
 

latch comparator

You can compress your figure then attached.
The ADC's reference voltage decide by it's input signal range.
 

Re: latch comparator

can you please elaborate more... my input signal range is 1.6V p-p...?????
 

latch comparator

If there is not PGA(program gain amplifier) adjust your input signal, the reference voltage is 1.6v. +Vref=0.8, -Vref=-0.8 maybe +Vref=Vrp-Vrn, -Vref=Vrn-Vrp.
Example you can design Vrp=0.8, Vrn=0. actual it decided by the common model voltage, usualy, common mode voltage is vdd/2.
 

Re: latch comparator

In differential dynamc latch comparator for pipelined ADC:
Vref is decided by signal range that u want to convert in digital ...i.e in b/w -Vref to +Vref.
which is the signal range of the o/p of opamp in any one stage in PL ADC except last stage.
suppose OPAMP o/p is linearly varying b/w 0.4 V to 1.4 V...then it is 2 V peak to peak differentially.
so here differential signal is varying from -1v(0.4v-1.4v) to +1v(1.4v-0.4v).....(-Vref to +Vref) which is 2v p-p differential.
so for PL ADC, two comparator trip points will be VL(-Vref/4)=-0.25v and VH(+Vref/4)=+0.25V.i.e.
Vin <VL, o/p of comparator =00
VL<Vin<VH, o/p =01
Vin>VH, o/p = 11
where Vin is differential signal varying from -1v to +1v

regards
anil
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top