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Fixed Point division in VHDL

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Hello dear,
I need algoritm/ guideline on fiexed point division in vhdl.
Secodnly, how to check that in how many cycles FPGA performs an operation(i.e. +, -, / etc.).
 

'paper and pencil' method is easy to design
you can google it
 

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    info_req

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info_req said:
Hello dear,
I need algoritm/ guideline on fiexed point division in vhdl.
Secodnly, how to check that in how many cycles FPGA performs an operation(i.e. +, -, / etc.).
Click to expand...

we al know the pensil and paper method. Can someone explain to us/me how to check the number of cycles an algorithm needs ?
thanks in advance.
 

can't be used lmp in stand ??
 

There're a lot of algorithms available for division in Hardware.

Try the Newton Raphson Algorithms.
 

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