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FSM Design Query.....Please help

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amandeep_pec

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Design a FSM (Finite State Machine) to detect more than one "1"s in last 3 samples.
For example: If the input sampled at clock edges is 0 1 0 1 0 1 1 0 0 1
then output should be 0 0 0 1 0 1 1 1 0 0

And yes, you have to design this FSM using not more than 4 states!!


Please help me solve this problem.......

thanks in advance....!!
 

The problem is simple... you can have 4 states...

S0--when you have zero 1's
S1--when you have one 1'
S2--when you have two 1's and
S3--when you have three 1's

Initially you start from state S0... whenever you encounter a 1' you go to next state i.e S0 to S1 or S1 to S2 etc... whenever you encounter a 0' you go to the previous state i.e S1 to S0 or S2 to S1 etc...

you can give output as one states S2 and S3...
 

    S

    S170410513

    Points: 2
    Helpful Answer Positive Rating
I have some confusion which I summarise here:
Input 0 1
S0: Initial S0/0 S1/0
S1 S2/0 S3/1
S2 S0/0 S3/1
S3 X S3/1

Could someone please help me to fill this state.S2/0 and S2/1 states are looking to be feasible [for 101 , this state should be S2/0,for 011 S2/1].
My opinion is that this state machine cannot be designed using 4states...Correct me if I am wrong...
 

hey for this one no need to go for fsm design . if u use one shift register u can get very easily
 

mallikmarasu said:
hey for this one no need to go for fsm design . if u use one shift register u can get very easily
Click to expand...

question is just for an FSM design.....
 

I have a problem here:

Lets have an input string 11001:
Output 0 1 1 0 1 (last one is wrong)
Q0 --> Q1 --> Q3 --> Q1 --> Q2 --> Q1
 

deh_fuhrer

You are right. What about this new state diagram?.
 

Thanks a lot for this FSM.....(I take my words back...)
 

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