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fixing setup violation using clock skew

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asicengineer1

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Hi,
would it be possible to remove setup violation by introducing clock skew purposefully in the design i.e. if the setup window is effectively pushed a little bit further only to that part of the flow where there is a setup violation?
 

Hi,

The answer is yes.but one should use this if these is small amount violation in that path but if u have huge amount of violation don't do this .

regards,
ramesh.s
 
This should be ok, but you may end up with hold violation. So beware…:wink:
 

Is there any other way of fixing setup violations in P&R flow ?
 

Reduce data path delay as much as possible. There are few techniques for that like

~ Up/down sizing cells
~ Adding/removing buffers
~ Changing placement of cells (except F/F after CTS)
~ Decreasing crosstalk delay by spacing/widening routing
etc…
 
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    asicengineer1

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    ivlsi

    ivlsi

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Ya you can add skew in the clock to remove the set up violation but it should be done only if the next path is having the more positive slack ..
But you should be careful while doing this because it may cause hold violation
 

Hi rake and shelk,

Could you explain a bit more on why this may cause hold violation? on which DFF?

Thank you very much!
 

There may more than one path through the combinational logic between the two FFs. We consider the maximum delay path between the two FFs for setup and minimum delay path for hold violations. So, if we increase the positive skew, we can avoid the setup violation with respect to the maximum delay path. But this may affect the hold requirement of the minimum delay path if the skew is very large or if the data required time to avoid setup and hold violation are very closed to each other.
 
ya
This can be surely done. Having 3 FFs adjacent to each other and if there is slack positive between the first FFs and if slack is -ive between other two, then the clock for the first flop can be made faster and the clock for the third flop can be made slow. This way we can increase the setup window.
 

If we increase the positive skew then the capture edge will be delayed so we can improve set up .
But at the same time the data has to be hold for long time for the first flipflop i.e , the hold time is increased so there are chances of hold violations.the skew time will be added in the hold time for the first ff.
.
 

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