Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to design PFD in Charge Pump PLL?

Status
Not open for further replies.
S

sandip_micro

Junior Member level 1
Junior Member level 1
Joined
Feb 27, 2007
Messages
18
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,283
Activity points
1,381
Hello friends
I want to ask whats the design procedure of Phase Frequenct Detector Block?
In PFD block we saw 2 D Flip Flops and one AND gate.
Input signals are: REf and fedback and RESET
Output singals are : UP and DN
If the VCO Freq=200 MHZ
Input Freq Range=3 MHZ ~800 MHz
 

just refer to the johansson pfd since your frequency range is very high. i mean that for the pdf to operate properly at a high frequency the delay through pfd must be less. you can refer to johansson's paper in JSSC


amarnath
 
Heel Amaranath
I want to know the general Design Procedure of PFD Block?
May be i/p freq=100MHz
Then how to start?
Do u have any PDF which explains the design of PFD block?
 

the pfd is just two d flip flops and a nand gate to reset both of them, size the transistors accordingly. Also do simulations do find out the width of the dead zone and then set the reset path delay slightly greater than the dead zone width.


amarnath
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top