Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to simulation Verilog HDL model using HSPICE?

Status
Not open for further replies.
RDRyan

RDRyan

Full Member level 2
Full Member level 2
Joined
May 24, 2007
Messages
132
Helped
21
Reputation
42
Reaction score
3
Trophy points
1,298
Location
China
Activity points
1,976
hspice .hdl

I have made a RTL model with Verilog HDL. My question is: Can we transfer Verilog RTL model to netlist that can be run by HSPICE? which EDA tools do I need? and how to do it?

Thanks very much!

Ryan
 

hspice .hdl cadence

Spice does not run verilog. Spice can run VerilogA. To run this you need mixed signal environment like AMS or ADMS
 

    RDRyan

    RDRyan

    Points: 2
    Helpful Answer Positive Rating
.hdl hspice

thanks for your comment.

And can we transfer Verilog HDL model to EDIF files, and use other tools (like viewdraw) to open it, then use viewdraw to create netlist that can be run in hspice ?

Ryan
 

hspice cadence ahdl model

Cadence can do this job
 

    RDRyan

    RDRyan

    Points: 2
    Helpful Answer Positive Rating
Thank you, I will try to use cadence.
 

In Cadence ADE, you can use hspiceverilog simulator to simulate verilog+schematic.
1 create a cell contain verilog file(using functional view)
2 create schematic view of test_bench cell connecting verilog cell and schematic cell.
3 create config view for test_bench cell
4 Open config view of test_bench cell, then open ADE to simulate
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top