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How many files does Xilinx tool generate for each VHDL file written?

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vinodkumar

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Hi
iam using xilinx tool for synthesis .can i get info reg how many files does the tool generate for each VHDl file written,plz suggest me docs to know what each file do.
becoz with this info i can understand actually what is internally going on step by step.

like in C language .C,.obj,.exe,.bak files.

bye....
 

Xilinx doubt

Hi Vinod
U can find this information in xilinx's tools guide. Though the info is not presented as such, the documentation of each tool (ngdbuild, par, trce etc) does specify what input files it take and what output files it give. It also gives u idea that of all the o/p files which are logs & which is what etc.
 

Xilinx doubt

I agree with abhi, you can have a look in tools guide. but at the same time you must have to look on xilinx site on "Development System Reference Guide"
(dev.pdf)
This pdf will give a description of all the input files used and the output files generated by the program(ISE).

Thanks,
Sachin
 
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