Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How many files does Xilinx tool generate for each VHDL file written?

Status
Not open for further replies.
V

vinodkumar

Full Member level 5
Full Member level 5
Joined
Oct 5, 2006
Messages
251
Helped
12
Reputation
24
Reaction score
3
Trophy points
1,298
Location
hyderabad
Activity points
2,822
Hi
iam using xilinx tool for synthesis .can i get info reg how many files does the tool generate for each VHDl file written,plz suggest me docs to know what each file do.
becoz with this info i can understand actually what is internally going on step by step.

like in C language .C,.obj,.exe,.bak files.

bye....
 

Xilinx doubt

Hi Vinod
U can find this information in xilinx's tools guide. Though the info is not presented as such, the documentation of each tool (ngdbuild, par, trce etc) does specify what input files it take and what output files it give. It also gives u idea that of all the o/p files which are logs & which is what etc.
 

Xilinx doubt

I agree with abhi, you can have a look in tools guide. but at the same time you must have to look on xilinx site on "Development System Reference Guide"
(dev.pdf)
This pdf will give a description of all the input files used and the output files generated by the program(ISE).

Thanks,
Sachin
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top