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How to calculate load regulation, line regulation and settling time from the graph?

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rekha410

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i am doing project on ldo.for this one i plotted load regulation and line regulation and also i did transient analysis.but i dont know how to calculate load regulation ,line regulation and settling time from the graph.....please help me...:cry:

Added after 6 minutes:
 

load regulation

For load regulation sim

Give a step current load which changes from 0 to max current spec.
The output waveform will give you both settling time due to current pulse as well as load regulation.
Find the difference in the regulator output with no laod and max load. Divide it by the max load gives the load regulation. The settling time requirement depends on the accuracy of the system for which u are designing the ldo. Suppose it is 12bit. Then find the time taken by the ldo to settle within 0.5lsb at 12bit level.
Similarly you can find line regulation and settling time with load step by giving a pulse

v(t) =Vin (min) t< t1
Vin(max) t2<t<t3
Vin(min) t>t3
make sure that t3 -t2 is large compared to the settling time spec.


hope this helps
fred

ps you can refer to TI's application notes on LDO for details
 

    R

    rekha410

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Re: ldo

thank u for the reply...for transient analysis i hav given current pulse from 0 to 50mA pulse width=50u and period=100u.for this excitation i plotted output voltage.from this graph how to measure settling time.i am doing this project on cadence tool. settling time means what for ldo...?please help me..
 

ldo

Baiscally it means the LDO should settle within its accuracy requirement. Normally this wont be stringent as the output of LDO will be acting as power supply.
Suppose you have a output accuracy requirement of say 3.3 +/- 0.2v then see the time required for the LDO to settle within this range.
 

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    rekha410

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Re: ldo

thank u fredflinstone.......How to select feed back resistors for ldo......
 

ldo

select Rf and Ri such that the quiescent current is low and the pole due to the fb resistors and the input cap of the error amplifier is at a much higher frequency compared to the ldo UGF. I would suggest you refer Prof. Rincon Mora's LDO thesis. You can downlaod it for free from his site.

rgds
fred
 

    R

    rekha410

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Re: ldo

I want to simulate a LDO, who can help me for simulation: transient response, frequency response, ...How can determine R(on) of Pass element. I am using Hspice for simulation.
 

ldo

correct, we have to determine the load and line regulation like that only
 

Re: ldo

Thanks fred for the reply........

regds
Rekha
 

Re: ldo

For ldo i am getting good phase margin(80deg) and gain(76db).but iam not getting good transient response(getting spikes in volts)............what factors(i.e GBW,phase margin)should be improved to get spikes in millivolts
 

ldo

Is the spikes settling down or is it oscillating? What is UGF (unity gain frequency) of ur LDO? Because if ur UGF is low then the ldo will take time to respond to the change in line/load.. so need to have good UGF.
Also what value of ESR are you keeping? ESR value can also degrade your transient response if the ESR is quite high.
 

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    rekha410

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Re: ldo

i am getting spikes magnitude in volts(>4v).i want spikes magnitude in milli volts.for this what parameters should be improved..................please give me reply as soon as possible.............
 

ldo

As I told you before, my guess is that this is because of the voltage drop across the esr of the output load capacitor. If you can keep a high frequency bypass capacitor ( cap with low esr) in parallel with the output load cap then the spikes should reduce.
Can you provide a snapshot of your ldo schematic? it will be easier for me to help you then.
 

Re: ldo

I hope you are using capacitor at the regulator output..if not you will see huge transient voltage dip! otherwise your regulator should be faster than load switching speed!
what is the rise and fall time of your load current?

hope it helps
 

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