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How to synthesis a VHDL code with real type?

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mmoctar

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I have a vhdl code with real type, I try to synthesis it on ise but I have problem with real type, I don't know how to do with...is someone have an idea..
 

Real synthesis

hi

plz follow the link for some info on how to write applns including REAL DATA TYPES...it'll help u to some extent

h**p://www.vlsibank.com/sessionspage.asp?titl_id=8792

n ya dont forget to say thnx if u find it useful.....hehe ...cheers

thnx
 

    M

    mmoctar

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