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Let us say, you have a huge combinational logic between two flops in your design. If this combo logic take more time than your clock period, then this can be considered a multi cycle path, provided this doesn't violate the functionality of the design.
Eg. Clock Period is 10ns, Combinational delay is 16ns. In this case, if it is acceptable for the functionality, you can define a multi cycle path of 2.
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