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Bandgap reference transient analysis

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chungming

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Hi ~~

I have a question about bandgap reference
Like attached picture
This is my transient analysis result (simulate vdd off and on conditions)
Why the bandgap voltage overshoot is so large?
(regardless there has start up circuit or not……)
My opamp is well designed.
(gain 80dB, phaseMargin 70, UGF 700kHz ,slew rate 0.8M V/s
and bandgap loop gain 80dB, loop phaseMargin 65, loop UGF 350KHz)

Thanks ~!!!!!
 

may be your supply voltage rise too fast ,
and the UGF is so limited. but in fact , the supply voltage may not rise so fast.

how about supply voltage rise in about 10uS
I think it will be better.
 

rfzheng said:
may be your supply voltage rise too fast ,
and the UGF is so limited. but in fact , the supply voltage may not rise so fast.

how about supply voltage rise in about 10uS
I think it will be better.
Click to expand...

rfzheng thanks for your reply ...
but this didn't work......
i try to lower opamp's gain, the transient respose is better
the VBG tran peak value lower to 1.8V.
But i can't understanding ... WHY ..... :cry:?
 

Why the bandgap voltage overshoot is so large?
Click to expand...
that's not overshoot !
overshoot is generated from closed loop response.
but in ur case, just after VDD ramp up, ur OP is saturated !!! so the loop is
"break", it's in open loop state. This kind of bandgap architecture suffer from this
phenomenon. u need to slow down the response, or reduce output resistance of node VBG
 
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    chungming

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    woai

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Btrend said:
that's not overshoot !
overshoot is generated from closed loop response.
but in ur case, just after VDD ramp up, ur OP is saturated !!! so the loop is
"break", it's in open loop state. This kind of bandgap architecture suffer from this
phenomenon. u need to slow down the response, or reduce output resistance of node VBG
Click to expand...

thank you Btrend ~

But how to slow down the response ?
Could you please give me some advice .
And you said "This kind of bandgap architecture " , do you means opamp based bandgap reference ?
thank you!
 

I have an other question: what the first Opamp do(pin 1,8,4,2,3) and the second Opamp?
Click to expand...
my suggestions:
(1) ramp up ur power supply using PWL(0 0 100u 3.3)
(2) add some capacitor in the right leg which connect to Vinn of the OP.
 

thank you Btrend
I will try ~!! :D
 

I think this is not overshoot .
This effect is simply due to the capacitor between the output node and VDD which is dicharged when the circuit is powered-down . Therefore , when the VDD is powered up , the capacitor takes some time to have some drop between its two terminals.
Try to decrease the capacitance between the output and VDD , and increase the capacitance between the output and ground.
 
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    woai

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It is not overshoot.
Only you power supply raise too fast, and you bandgap cann,t settling at that time. Tere are large capacitor at net VBG, so it cann,t settling quickly. You can check other net point whether settling at that time.
 
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    woai

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HI,chungming
there are two ways to reduce this kind of overshoot
1) get rid of the capacitor betweent VBG and VDD, since your supply voltage shut downto zero ,then this capacitor will discharge
to zero, but when your supply voltage rise to 3.5v in a fast
transient, the voltage of this capacitor will not change suddenly,so
VBG will rise will supply voltage formeDd this kind of overshoot.

2)supply voltage in the real word will not rise so fast ,so give a little time to the supply voltage to 3.5V
 

What is the rising time of supply voltage in real world ?
 

i remember the supply ramps up time is from 1us ~ 1ms
 
is that psrr good in this design?
 

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