Questions about poly layer in CMOS layout

I have two questions regarding CMOS layout

1, when I use poly layer to connect two transistor gates together(the distance is not long), is it OK? or I'd better connect the two gates together through metal layer?

2, I want to draw the poly layer over the PDIFF or NDIFF layer, ( for example in an inverter, I draw a PDIFF around the NMOS, and then add some contacts on the PDIFF for guard ring, but I leave some PDIFF part without guard ring for wiring across it). I am not sure if it is a problem?
Because once I read that the poly layer across Diffusion layer are usually inteprated as gates, so in general people should avoid that?

Re: CMOS layout?

katrin said:

1, when I use poly layer to connect two transistor gates together(the distance is not long), is it OK? or I'd better connect the two gates together through metal layer?

Click to expand...

The problem in poly interconnects that it has higher resistivity than metal, however if the distance is so close it may be better as u won't need contacts and thus get rid of contact's resistance, so i think u need to check process documents and decide which is better and also u need to know whether the delay at this gate is critical or not if there is no concern from the delay, i think it's ok to use poly interconnect.

Re: CMOS layout?

katrin said:

2, I want to draw the poly layer over the PDIFF or NDIFF layer, ( for example in an inverter, I draw a PDIFF around the NMOS, and then add some contacts on the PDIFF for guard ring, but I leave some PDIFF part without guard ring for wiring across it). I am not sure if it is a problem?
Because once I read that the poly layer across Diffusion layer are usually inteprated as gates, so in general people should avoid that?

Click to expand...

I don't think you should leave some PDIFF part without guard ring for wiring across it. You can add guardring around PDIFF and use high level layer metal for wiring across guarding.

Re: CMOS layout?

RDRyan said:

katrin said:

2, I want to draw the poly layer over the PDIFF or NDIFF layer, ( for example in an inverter, I draw a PDIFF around the NMOS, and then add some contacts on the PDIFF for guard ring, but I leave some PDIFF part without guard ring for wiring across it). I am not sure if it is a problem?
Because once I read that the poly layer across Diffusion layer are usually inteprated as gates, so in general people should avoid that?

Click to expand...

I don't think you should leave some PDIFF part without guard ring for wiring across it. You can add guardring around PDIFF and use high level layer metal for wiring across guarding.

Click to expand...

So you mean it is better to have guard ring all around the devices when it is possible instead of leaving some PDIFF part without guard ring only for wiring purpose? Is it better for the circuit's performance?

Re: CMOS layout?

katrin said:

I have two questions regarding CMOS layout

1, when I use poly layer to connect two transistor gates together(the distance is not long), is it OK? or I'd better connect the two gates together through metal layer?

2, I want to draw the poly layer over the PDIFF or NDIFF layer, ( for example in an inverter, I draw a PDIFF around the NMOS, and then add some contacts on the PDIFF for guard ring, but I leave some PDIFF part without guard ring for wiring across it). I am not sure if it is a problem?
Because once I read that the poly layer across Diffusion layer are usually inteprated as gates, so in general people should avoid that?

Click to expand...

Hi katrin

Preferably poly routing is not done because of its high resistance. But, if the distance is not very long, you could still go ahead with the same, like in the case of an inverter where u could keep the pfet close to the nfet, that should be fine.Otherwise, poly routing is definitely not a good practice.
You need not enclose the diffusion layer with guardring on all the sides unless it is some noisy/critical device / if matching is expected. It wud unnecessarily increase the area.

Regards
Brittoo

CMOS layout?

I agree with Brittoo.
It's not nessary to add guardring in a Inverter. But in analog design, if you are very care about noise and you should add guarding around the device. then use metal for interconnect. It will be better for circuit's performance.

CMOS layout?

The poly resistance is larger than metal but in salicide process it is less than 10 ohm per_square. gate poly(not resistor poly) is about 30 ohm in normal no_salicide peocess. And the poly cross the diffusion area that generate a parasitic transistor. and the gate is near the substrate. the line loading and noise from subatrate will be increase.
Whether you can do that determined by your design and application.

CMOS layout?

Polu routing - for short interconnect and for not-so-important connections (like slow digital) it is ok. For example most of digital libraries use poly routing which is way sloppier than what you'd ever do.
Regarding PDIFF and NDIFF and poly - yes they form device BUT - most of extractors also use other layers to recognize devices. (Active or whatever they call it depending on technology and P/Nwells) if stretch of Poly over guardring is recognized as device it is not a good written extractor.

Re: CMOS layout?

1.As poly create parasitic transistors and have higher resistivity then metal ,conectivity by metal is preferable but for very short distance there is no as such problem for connecting by poly.

2.Your question regarding gaurd ring is much serious when u r doing analog layout cause in that case you cant leave any part of PDIFF ungaurded but in case of inverters your version ll be OK.

Re: CMOS layout?

secondlife said:

2.Your question regarding gaurd ring is much serious when u r doing analog layout cause in that case you cant leave any part of PDIFF ungaurded but in case of inverters your version ll be OK.

Click to expand...

So in the analog layout, I should draw the guard ring all around the devices.
But usually I only add the guard ring for two sides for the device, and leave the other two sides unguarded for metal routing. Because it is easier to route the signal line also on metal one.
Are there any serious consequences, for example, some thing like large substrate noise?

Re: CMOS layout?

katrin said:

secondlife said:

2.Your question regarding gaurd ring is much serious when u r doing analog layout cause in that case you cant leave any part of PDIFF ungaurded but in case of inverters your version ll be OK.

Click to expand...

So in the analog layout, I should draw the guard ring all around the devices.
But usually I only add the guard ring for two sides for the device, and leave the other two sides unguarded for metal routing. Because it is easier to route the signal line also on metal one.
Are there any serious consequences, for example, some thing like large substrate noise?

Click to expand...

hey katrin

Lke as i told u earlier, u need not add guardring on all the sides of a device blindlly. If it is a noisy device, then u need to protect ur circuit from this guy, so u need to enclose this device completely in a guradring. Again, for matched devices like the differential pair wherein matching is critical, complete guardring is preferred. U need to know which are the critical devices in your layout and add guard rings accordinlgly.
Every guard ring would have its effect upto certain distance like 15u or 30u , process dependent. So, you could get this info and add guardrings every 15u/ whatever distance accordingly for not-so-critical devices.

Regards
Brittoo

Re: CMOS layout?

Brittoo said:

katrin said:

secondlife said:

2.Your question regarding gaurd ring is much serious when u r doing analog layout cause in that case you cant leave any part of PDIFF ungaurded but in case of inverters your version ll be OK.

Click to expand...

So in the analog layout, I should draw the guard ring all around the devices.
But usually I only add the guard ring for two sides for the device, and leave the other two sides unguarded for metal routing. Because it is easier to route the signal line also on metal one.**broken link removed**
Research Projects, Institute of Microelectronics, University of Ulm
Are there any serious consequences, for example, some thing like large substrate noise?

Click to expand...

hey katrin

Lke as i told u earlier, u need not add guardring on all the sides of a device blindlly. If it is a noisy device, then u need to protect ur circuit from this guy, so u need to enclose this device completely in a guradring. Again, for matched devices like the differential pair wherein matching is critical, complete guardring is preferred. U need to know which are the critical devices in your layout and add guard rings accordinlgly.
Every guard ring would have its effect upto certain distance like 15u or 30u , process dependent. So, you could get this info and add guardrings every 15u/ whatever distance accordingly for not-so-critical devices.

Regards
Brittoo

Click to expand...

thanks Brittoo,

I think I understand the point. So I need to take care of the sensitive devices where matching is important such like current mirror. On the other hand, for the inverter, the complete guard ring is not necessary.

CMOS layout?

for first question
useing poly is much better than metal
for the second
it's true a poly over a diffusion acts as a gate

Re: CMOS layout?

For question 1:

I think you better used metal to connect poly because poly give much much higher resitance. Transistor gate in analog design very sensitive and preferable to connect it with metal.

Re: CMOS layout?

katrin said:

I have two questions regarding CMOS layout

1, when I use poly layer to connect two transistor gates together(the distance is not long), is it OK? or I'd better connect the two gates together through metal layer?

2, I want to draw the poly layer over the PDIFF or NDIFF layer, ( for example in an inverter, I draw a PDIFF around the NMOS, and then add some contacts on the PDIFF for guard ring, but I leave some PDIFF part without guard ring for wiring across it). I am not sure if it is a problem?
Because once I read that the poly layer across Diffusion layer are usually inteprated as gates, so in general people should avoid that?

Click to expand...

1, depending on your application ; i think it is ok in digital circuits but you might take care of the gate current if you use very deep submicron technologies i.e below 65nm for example , in RF circuits ; the gate resistance plays a very important role in limiting the performance, you should minimize it as you can , some researches show that the gate resistance is the bottle neck for multi-GHz RF circuits

2, i think that is true, a poly over diffusion interpreted as a transistor, i think it is the way you can place 2 transistors in schematic and then in layout you can merge them into one with fingers

Re: CMOS layout?

hi.. i'm new here.. i'm undergradute student taken vlsi n analog ic as my elective subj.. i want to ask if any one can advice me, give some ideas about my final year project. my project tittle is about the layout design techniques for analog vlsi ccts.. very appriciate for the reply an any comments..


thanks

Re: CMOS layout?

Hi

Regarding the first topic. It's absolutly ok to wire short distances in poly
If you change the layer to another poly or the first metal layer, it's not
sufficient to compare just the specific resistance of the wiring level, always
watch the contact resistance as well. Contacts usually have an unbelievable
bad resistance, so watch out here. Besides that, keeping the wiring in poly
keeps the upper layers for connections to the stages around. Put your devices
gate to gate, place the gate contact right in the middle for optimal connection.
If your devices are wide, use fingering, if the fingerlength is still critical connect
both sides of the devices.
About the second topic. One should never wire poly over diffusion as this is
forming a parasitic device, whether a LVS runset is checking for that or not.
Proper use of substrate and well contacts close to n and p-Fets offer sufficent
protection for digital logic functionality. Analog circuits are much more vulnerable
of course. If your technology offers isolated devices, you could use such devices
or use dual or triple guardrings with good connection to the power supply for
normal devices. However such guardrings offer little protection against massive
substrate noise (e.g induced by pad undershoots -> massive charge injection
into the substrate). If this is happing for your design, keep enough distance
to the i/o or clock pads, especially if your design includes parts with weakly
driven nodes ...

Best Regards

Andi

Re: CMOS layout?

for short distance it may not mater if u use poly inter connect.but I u need a option to change the gate connection later without having to release poly mask layer u can use metal inter connect.

usually poly over diffusion will be treated as mos in the process of creating mask. so don't use this.

hope this helps You