[Let's discuss] LOCKUP Cell in SCAN chain.

lock up latch

Hi, everyone,

We know, DFT Compiler inserts lockup latch between adjacent scan FFs if they are triggered by different clocks and the test clock waveforms are the same.
Use the command set_scan_configuration –add_lockup ture

However, in this case, how can we set false path when doing test mode STA ?

Now, we use the test clock that can be controled on top level. If we don't want to insert lockup cell. Does it means we should control the test clock timing properly?

Is there something we should think about ?

dft lockup

If you don't let the tool insert the lockup-latches, you will have to tightly control the inter-clock skew very carefully within your CTS flow.

I can't think of any reason you'd have to worry about them during STA. They pose no timing problems, because they're in the scan chain - where they help with the possible hold time problems.

John
**broken link removed**

lockup cell

Thanks, John.

You are right. But my test clock can be controlled on top level. They are external clocks. Do you think it is possible to control the timing for a big SoC design ?

About lockup cell:
Now, in my design, every scan chain has only one test clock. So I found no lockup cell inserted in the scan chain.
However, if an inverter located between two scan dff's clock input, the luckup cell is needed.
However, dft compiler does not insert lockup cell. Why? How can I make it insert lockup cell?

Thank you !

dft_guy said:

If you don't let the tool insert the lockup-latches, you will have to tightly control the inter-clock skew very carefully within your CTS flow.

I can't think of any reason you'd have to worry about them during STA. They pose no timing problems, because they're in the scan chain - where they help with the possible hold time problems.

John
**broken link removed**

Click to expand...

what is lock up latch

Oh, sure, by default DC will not put in a lockup latch for a single clock block-level scan chain. But there is a switch you can use to insert a lockup at the end of each chain, which is probably a good practice if you're going to be stitching them together at a higher level of hierarchy. I'd hve to lookup the name of the switch...

However, it also sounds like you're asking about clock inversions in your scan chain. DC will, by default stitch up all the negedge flops together in the front of the scan chain, before all the posedge flops, so you will have exactly one place where that inversion takes place, and you don't need a lockup there.

There should never be a place in your scan chains where a posedge FF feeds a negedge when a tool does the stitching. However, if you create that situation manually, adding a lockup may or may not help. Be careful.

John
**broken link removed**

why put lockup latch at the end

Thanks, John.
1. In my design, there is no negedge flip-flop, only posedge flip-fllop. However, some logic can be around posedge flip-flop, such as inverter. So an inverter and a posedge flip-flop equal to a negedge flip-flop. In this case, no negedge flip-flop, but lockup cell needed. DC can not find negedge flip-flop. How to insert lockup cell ?

2. You said :

There should never be a place in your scan chains where a posedge FF feeds a negedge when a tool does the stitching. However, if you create that situation manually, adding a lockup may or may not help. Be careful.

Click to expand...

You means the flip-flop triggered at negative edge of test clock must be followed by the flip-flop triggered at positive edge of test clock. I know it can get long test period.

Now , I have 3 cases :


Can you intruduce how to insert lockup cell in the first 2 case?

Thank you !!!

dft_guy said:

Oh, sure, by default DC will not put in a lockup latch for a single clock block-level scan chain. But there is a switch you can use to insert a lockup at the end of each chain, which is probably a good practice if you're going to be stitching them together at a higher level of hierarchy. I'd hve to lookup the name of the switch...

However, it also sounds like you're asking about clock inversions in your scan chain. DC will, by default stitch up all the negedge flops together in the front of the scan chain, before all the posedge flops, so you will have exactly one place where that inversion takes place, and you don't need a lockup there.

There should never be a place in your scan chains where a posedge FF feeds a negedge when a tool does the stitching. However, if you create that situation manually, adding a lockup may or may not help. Be careful.

John
**broken link removed**

Click to expand...

what is lockup flip flop

DC can not find negedge flip-flop. How to insert lockup cell

Click to expand...

Semantics - DC doesn't look for negedge flops per se, it looks at the clock path, and determines whether the flop in question is activated on the posedge or negedge of the defined clock. Unless somebody convinces me otherwise, I stand by the fact that DC will not line up negedge activated after posedge activated flops in a scan chain.

As for the first two of your three cases, assuming your test clock is defined as a positive pulse (starts at zero, goes high, then low), number two does not need a lockup latch.

As for number one, I'm hoping you don't end up with this within a scan chain, but if you do, a lockup latch can hold the data for only a half-period, in other words, until the negative edge of the clock, so as long as your clock skew between the clock at the lockup latch and the clock at the next FF (activated on negedge), you'll be ok.

The best way to visualize this, really, is to code up an example and simulate it.

John
**broken link removed**