Which HDL is preferred by the companies for industrial application, VHDL or VERILOG?

Hi friends,
Which HDL is preferred by the companies for industrial application, VHDL or VERILOG?
and why? Or is there no such preferences?Please answer.

Thanks in advance

verilog vs vhdl

Hi
Verilog is used more than compared to VHDL .
its may be due to following reasons ..
(1) Very Easy (construct like C ) for begineers than VHDL..
(2) More Library available
(3) More features for verification.

vhdl versus verilog

Hi
In my point of veiw as a person familiar with C++ programming , Verlilog is better than VHDL, but for making a fair decision between Verilog and VHDL check out the following pdf :

Verilog HDL vs. VHDL for the first time user
**broken link removed**

here is the conclusion of that paper :

VHDL was developed (for the US DOD) to provide a consistent modeling language for the documentation of digital hardware designs. The language was never intended to be used to do actual design. However, to maintain a supposed competitive advantage, individual EDA companies exerted considerable influence, resources and dollars to force the language to become a design language. These same EDA companies implemented their own semi-unique versions of the language at different stages during its development. This means VHDL models that were developed on one system, may not run on a different system. The language is difficult to learn and even more difficult to use. It is extremely verbose, especially at the gate level, when timing information is specific and considerable. VHDL’s verbosity causes severe memory problems when trying to simulate medium to large designs. ASIC vendors have been very reluctant to provide VHDL gate level libraries that include full timing because of the size of the models and the abnormally long simulation times associated with validating a relatively simple design. The framers of VHDL were driven by the US DOD, which has no material interest in design productivity. VHDL’s complexsyntax interferes with design productivity and does not offer any strategic advantage that would improve the quality of the design. This essentially undermines the basic strength of VHDL, productivity achieved via a methodology based on top-down-design.

Verilog HDL has been developed and will continue to evolve to address the needs and commercial applications of the design community that has made it the most successful language in use today. The design community has invested almost 20 billion dollars in Verilog HDL and related tools over the last 8 years. The ability to address higher level language constructs are well supported in the language, along with its rock solid structural (gate and switch level) strengths. As long as designers and their companies have to get high quality innovative products to market in the time sensitive world in which we all compete, Verilog HDL will continue to be the dominant solution. Almost every major computer manufacturer, system developer, ASIC and semiconductor manufacturer uses Verilog HDL as their modeling language.

For the first time HDL user the selection of Verilog HDL as your modeling language will be a very wise decision. It will mean there are a number of tools available from schematic entry to synthesis to simulation at various price ranges and on numerous platforms from PCs to mainframes. There are also numerous libraries available from a variety of sources that support full timing based models with all the necessary delay functionality required to meet your critical design needs. There is also a vast resource of Verilog HDL engineering talent that has had experience using the language for practical commercial design to provide critical assistance if it becomes necessary. There are many HDLs you can choose from but only one that has proven time and time again that it is the only choice for real designs.

I hope it helps you.

BR

vhdl vs. verilog

many companies will prefer Verilog.

Only Scientfic Research companies like ISRO prefer VHDL.

VHDL is also not easier to learn Verilog

Dinesh

difference between verilog and vhdl

Verilog is easier to understand and use. Verilog is the language of choice for industrial applications that required both simulation and synthesis. It lacks, however, constructs needed for system level specifications. VHDL is more complex, thus difficult to learn and use. However it offers a lot more flexibility of the coding styles and is suitable for handling very complex designs

Pls see the link for complete description
Verilog vs. VHDL: VHDL & Verilog Compared & Contrasted
Plus Modeled Example Written in VHDL, Verilog and C
h**p://www.angelfire.com/in/rajesh52/verilogvhdl.html

verilog vs. vhdl

Many many thanks to you all for giving such good answers.

What are the good and small projects that a begginer could do which have some real life use?

difference between vhdl and verilog

Do some IP in Verilog coding. i.e
Do Image processing, compressing such stuffs

It will be more usefull

Dinesh

difference between verilog hdl and vhdl

You can do filters like FIR,adder, multiplier, 8085, UART, PCI bus protocol.

-Ruta

difference between vhdl and verilog hdl

As far as I know all US based companies use Verilog and all the European based companies use VHDL. Like wise all universited in US teach Verilog and European Universitied teach VHDL . the difference is based on the comp. and there is no much diffence between the 2 language. A few more IEEE library are required of VHDL .. but i have personally never heard some one saying they r more comfortable coding in either of only lang!

Suresh

verilog versus vhdl

Recently, I worked in Europe for two large well known semiconductor companies. Both of whom were using Verilog 2001 and System Verilog.

Vhdl is used primarily for projects funded by the government and fits in with the designed by committee culture of such project rather than the verilog "nuts and bolts" approach. VHDL is also taught at a number of universities, probabably due to government funding of research. However, just about every company in the commerical sector uses verilog.

And don't kid yourselves...VHDL is COMPLETELY UNSUITABLE AS A SYSTEM MODELING LANGUAGE... You would have to be completely insane to throw away your copy of Matlab and C++ in favor of VHDL... On the other hand, Verilog doesn't pretend to be something its not... Instead, the philosophy of verilog is to make it easier to compile C++ together with verilog if system level models are needed.

that's why they are called "Hardware Description Languages"... VHDL and Verilog have only one goal... to describe and test hardware implementations... Personally, I would much rather write a testbench in Verilog than VHDL.. so in that sense, VHDL completely fails as a system language. Secondly, if I had to design a filter, or some other alogirthm, I'm not going to do that by coding HDL first! that would be completely ludicriuos! No, instead, i'm going to startup matlab or write some c-code. So let's stop pretending that VHDL is a system language... its not... nobody wants to model algorithms with a crippled ADA compiler that's been modified to model hardware implementations.. and thus you still need to use the proper tool for the job.... It exactly the same reason, that C++ makes a poor hardware description language... SystemC anybody?

If VHDL is a system language, then I hereby declare that everybody should stop programming in C++ and use only VHDL for everything! thus we can have VHDL device drivers, VHDL GUI's, VHDL Operating Sytems... VHDL matlab... VHDL everywhere... give me a break...

verilog hdl vs vhdl

As I see, the conclusion (h**p://www.angelfire.com/in/rajesh52/verilogvhdl.html) is:
"The choice of HDL is shown not to be based on technical capability, but on: personal preferences, EDA tool availability and commercial, business and marketing issues."
I have nothing to add to.

vhdl vs verilog hdl

thanks man for this review