khaila
Full Member level 2
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generated clock from mux
Supposed we have CLK.
A block need CLK/2.
In order to generate CLK/2 I used D-ff that its input is drived by its Qn.
Can I use this CLK/2 in my design??? so I will have two clock domains!
Does dividing the a CLOCK by sequential logic is permitted in ASIC design???
Supposed we have CLK.
A block need CLK/2.
In order to generate CLK/2 I used D-ff that its input is drived by its Qn.
Can I use this CLK/2 in my design??? so I will have two clock domains!
Does dividing the a CLOCK by sequential logic is permitted in ASIC design???