Questions related to Physical design: kindly help (Part 4)

26. how to do ILMs for timing optimization?

27. how to do Partitioning the Design?

29. What is AWE(Asymptotic Waveform Estimation) ?

30. why is power planning done and how? which metal should we usefor power and ground ring & strips and why?

31. how do we elimate slack if it occurs during First optimization stage (trial routing)?

32. How do we calculate the die size from cell count of our design?

33. Why Parasitics Extraction for only R and C ,why not L(inductor) ?

34. what are the output files after physical Design?

Re: Questions related to Physical design: kindly help (Part

ANS: 34 :
The output files after the physical design is the final layout in gdsii( Graphic Data System) .

Re: Questions related to Physical design: kindly help (Part

Please find my answers below

26. how to do ILMs for timing optimization?
A) ILM stands for Interface Logic Model. When faced with running STA on huge blocks we use ILMs of child blocks to run top level STA for better run times. ILMs essentially have just the input and output timing for a block and not the internal timing for blocks

27. how to do Partitioning the Design?
A) Depends on lot of factors like, size, logical hierrchy, timing, aspect ration. It varies from design to design

29. What is AWE(Asymptotic Waveform Estimation) ?
A) It is used for timing engines in tools like PT and Astro to calculate delays. Its more accurate than Elmore

30. why is power planning done and how? which metal should we use for power and ground ring & strips and why?
A) To supply power to evert part of the design. In general we use top levels since the resistance associated with those top layers is less

31. how do we elimate slack if it occurs during First optimization stage (trial routing)?
A) During estimation stage we estimate without net delays. If timing is not meeting we need to analyze and change the SDC or report to the front end teams.

32. How do we calculate the die size from cell count of our design?
A) We use 2 input NAND gate areaXcellcount+Macros area to caliculate the die size

33. Why Parasitics Extraction for only R and C ,why not L(inductor) ?
A) Since Digital IC run at low frequencies, the Inductance is not a big contributer. Hence we ignore it.

34. what are the output files after physical Design?
A) GDS, SDF, netlist etc

Hope it helps