How to fix Density errors in DRC?

drc poly density

Hi,
What's the best way to correct "Density" errors got from running DRC on certain layout?
What let them come originally? i.e. What's their important in reality??

Thanks,
Cheers,
--Knack

metal density fixes

Hi knack - there's many different way to fix density errors...

1. if it's metal density you can make the width of the metals set to more than minimum distance.

2. You can add dummy metal pattern as well and distribution must be equal.

3. If it's in block level just ignore it because once you instantiate your block on the top level all the density error will be gone because of more metal s and polysilicon used. But based on my experience I normally fix the density problem in the block level to make sure that it is drc clean.

4. You can add more substrate contacts and via contacts as the metal fill for the gaps.

5. This is the importance of density issues.Planarity -the difference in oxide heights for a given region on a design is an important factor affecting wafer yield. When a design has regions of low metal density, the oxide layer can sag considerably. Polishing does help improve planarity, but if metal density is particularly low, the amount of oxide sagging can be too great to overcome.

cheers,
fixrouter

Added after 4 minutes:

Also to add up the reason why you should fix the density errors in block level to make sure that you have improve the planarity on that level.

enjoy!

minimum density design rule check

we can wave this error at block level, but we need to fix it at chip level.


for min density---------
to fix this kind of error, if its only related to poly.....then you can put dummy poly strips or blocks ( strips preferred as small devices are effected at time of fabrication if a large body is arround them) and connect them to either vdd or vss.
first try to fill all the empty spaces where ever possible, at the same time try to be as much uniform as you can while placing poly strips as this will have a big impact on the yield.

if min density error is related to both diffusion and poly...........then try to place dummy transistors with large lengths ( fingering can be used) and connect to appropriate powersupply. each terminal (s/d/g/b) either to vdd or vss.


if its related to metal layer...........try increasing the width of the power rails first, then of the fast switching signals like clock. if you have some large spaces then put some metal strips there.

why to fix min density errors...............
if any metal layer or poly or diffusion layer is not uniformly distributed in that case at the time of fabrication blank spaces will be present at places where these layers are not present and at time of etching if this blank space is large enough, then some etchant will accumulate at these places and will effect the reliability to a great extent. so we need to fix these errors as well.


to fix max density errors...........
generally will come in picture
1) for higher metals..
reduce the width of the power rails and other signals.

2) in case of memories if you are using rings as the kind of power supplies.............and both horizontal and vertical rings are of the same metal.
in this case you can cahnge the metal slotting option or the spacing between the rings, small change in any of these will have a significant effect.( but again it depens on the macro size and ring widths....for small macro it will be difficult to fix.)

low metal pattern density issue

Leave it until full chip or block is checked

full chip drc issues

ahmad_abdulghany said:

Leave it until full chip or block is checked

Click to expand...

I guess it is always better to correct them at cell level. But however you can relax the DRC rules if the block is carrying huge cuurent by doing DRC with the chip option. There is a little bit of risk as these might come again in top-level since we did DRC using chip option at cell level.

Added after 48 seconds:

Whatever i mentioned was for correcting max density errors...

density + drc

I believe we should clear the drc at chip level .... as generally you will find suficient empty space there...

via density drc

deepak242003 said:

I believe we should clear the drc at chip level .... as generally you will find suficient empty space there...

Click to expand...

Empty space is never an issue in chip level as they always place dummy metals(through scripts) before the laff is sent to fab...

sagging in metals in analog layouts

sandeep_torgal said:

deepak242003 said:

I believe we should clear the drc at chip level .... as generally you will find suficient empty space there...

Click to expand...

Empty space is never an issue in chip level as they always place dummy metals(through scripts) before the laff is sent to fab...

Click to expand...

If the density violations are less we can use part of this empty space to clear the density bcause the dummy filling around the active block is not desired due to performance constraint..

Added after 5 minutes:

and i believe it is gds that is sent to fab for fabrication.....
nyways what is laff??

fixing geometric drc with encounter

Regarding the density violations am not able to make out what
you intend to convey. Can you plz elaborate.

laff is lisp archival file format. We can convert laff to gds and viceversa. gds is the final thing which will be sent to fab. Can somebody throw more light what info will the gds contain. Is it instructions for the mask instruments ?

view laff layout files

sandeep_torgal said:

Can somebody throw more light what info will the gds contain. Is it instructions for the mask instruments ?

Click to expand...

GDS II stream format, common acronym GDSII, is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form.

converting laff to gdsii

Let me reframe the que : Can anybody throw light as to how the gdsii information is used in pattern generation. What are the steps from gdsii to tape-out.