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Program and Verify KO

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System.out

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xc3s400 status register

Hello,

While i program and verify a serial flash succesful, i program and verify S3-400 unsuccesfull, ISE tells me that it has 1981 differences.
FPGA also does not do what i want even that flash memory has been programmed fine.

Some help is appreciated. Thanks.
 

jtagclk frequency spartan3

Are you downloading with Xilinx iMPACT? Can you show us the full text output from iMPACT? Maybe it contains additional clues.

Does it always say "1981 differences", or does the number change randomly?

Is the board a new design of yours, or is it a commercial product?

Which download method (JTAG, slave serial, etc) and interface cable are you using?

"FPGA does not do what I want" - does it do anything? Is the DONE pin asserted?

What does "KO" mean in your subject line?
 

impact:395 - the number of difference is

echo47 said:
Are you downloading with Xilinx iMPACT? Can you show us the full text output from iMPACT? Maybe it contains additional clues.
Click to expand...

Code: 
Process "Configure Device (iMPACT)" completed successfully
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setMode -bs
GUI --- Auto connect to cable...
// *** BATCH CMD : setCable -port auto
AutoDetecting cable. Please wait.
PROGRESS_START - Starting Operation.
Connecting to cable (Parallel Port - LPT1).
Checking cable driver.
 Driver windrvr6.sys version = 8.1.0.0. WinDriver v8.10 Jungo (c) 1997 - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version = 810.
 LPT base address = 0378h.
 ECP base address = 0778h.
Cable connection established.
PROGRESS_END - End Operation.
Elapsed time =      1 sec.
Attempting to identify devices in the boundary-scan chain configuration...// *** BATCH CMD : Identify 
PROGRESS_START - Starting Operation.
Identifying chain contents ....'1': : Manufacturer's ID =Xilinx xc3s400, Version : 0
INFO:iMPACT:1777 - 
Reading C:/Xilinx91/spartan3/data/xc3s400.bsd...
INFO:iMPACT:501 - '1': Added Device xc3s400 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'2': : Manufacturer's ID =Xilinx xcf02s, Version : 15
INFO:iMPACT:1777 - 
Reading C:/Xilinx91/xcf/data/xcf02s.bsd...
INFO:iMPACT:501 - '1': Added Device xcf02s successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
Maximum TCK operating frequency for this device chain: 0.
Validating chain...
Boundary-scan chain validated successfully.
PROGRESS_END - End Operation.
Elapsed time =      1 sec.
// *** BATCH CMD : identifyMPM 
// *** BATCH CMD : assignFile -p 1 -file "C:/tmp/counter/counter_prom.mcs"
'1': Loading file 'C:/tmp/counter/counter_prom.mcs' ...
done.
// *** BATCH CMD : setAttribute -position 1 -attr packageName -value "(null)"
// *** BATCH CMD : assignFile -p 2 -file "C:/tmp/counter/counter.bit"
'2': Loading file 'C:/tmp/counter/counter.bit' ...
done.
WARNING:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
INFO:iMPACT:501 - '2': Added Device xc3s400 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
// *** BATCH CMD : Program -p 2 -v -defaultVersion 0 
Maximum TCK operating frequency for this device chain: 0.
Validating chain...
Boundary-scan chain validated successfully.
PROGRESS_START - Starting Operation.
'2': Programming device...
done.
'2': Reading status register contents...
CRC error                                         :         0
RESERVED                                          :         0
DCM locked                                        :         1
DCI Matched                                       :         1
legacy input error                                :         0
status of GTS_CFG_B                               :         1
status of GWE                                     :         1
status of GHIGH                                   :         1
value of MODE pin M0                              :         0
value of MODE pin M1                              :         0
value of MODE pin M2                              :         0
value of CFG_RDY (INIT_B)                         :         1
DONEIN input from DONE pin                        :         1
ID_ERROR                                          :         0
RESERVED                                          :         0
RESERVED                                          :         0
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 0111 0001 1000 0000 0000 0000 0000 
'2': Verifying  device...INFO:iMPACT:2495 - Readback Size is 1695744.
ERROR:Bitstream:98 - There are 2049 differences.
ERROR:iMPACT:395 - The number of difference is 2049
'2': Verification terminated.
done.
'2': Programming terminated due to errors.
PROGRESS_END - End Operation.
Elapsed time =     20 sec.

echo47 said:
Does it always say "1981 differences", or does the number change randomly?
Click to expand...

The number changes randomly.

echo47 said:
Is the board a new design of yours, or is it a commercial product?
Click to expand...

It is a design of mine.

echo47 said:
Which download method (JTAG, slave serial, etc) and interface cable are you using?
Click to expand...

I'm using Parallel cable III on Master Serial 3.3V Configuration, following Figure 4: Connection Diagram for 3.3V Master Serial Mode with Platform Flash PROM from XAPP453 (v1.1). JTAG is powered to 2.5V and resistors R_{par} and R_{ser} are assembled/soldered on the board.
iMPACT Boundary Scan detects devices fine.

echo47 said:
"FPGA does not do what I want" - does it do anything? Is the DONE pin asserted?
Click to expand...

I can program PROM and verify it. I can program FPGA, but verify fails. I masked the FPGA using a simple binary counter, but when looking those lines... it does not look like a counter, later on i found out that i was looking the wrong lines.

FPGA does not do what the code says to do (I have checked the code with a S3 Demo board i have).

Yes, pin DONE is set to 2.59 V

I have also checked all power lines, and they look fine.
VCCO is set to 3.3V
VCCINT is set to 1.26V
VCCAUX is set to 2.5V

echo47 said:
What does "KO" mean in your subject line?
Click to expand...

To Knock Out.
It is the opposite of O.K. (being satisfactory or in satisfactory condition;)

Thanks :D

Added after 1 minutes:

When programming PROM with iMPACT, i get this message when loading the bitcode into the FPGA:
Code: 
'1': Starting FPGA Load with Prom Data...INFO:iMPACT:563 - '1':Please ensure proper connections as specified by the data book ...

Added after 51 minutes:

I see that DONE pin is set to 0V when programming, then goes up to 2.5 V and then it goes back to 0V to verify, then when the error barfs, it stays up to 2.5 V

Added after 1 minutes:

I have already tried it without 68 ohm resistors. It even has more differences. Could the FPGA be damaged ?
 

The DONE signal indicates that the FPGA has validated the bitstream CRC, so the FPGA should be running fine, even if iMPACT is having trouble verifying it.

The random verification errors suggest that iMPACT is somehow having trouble reading the FPGA. Your Parallel Cable III connection may have marginal signal quality. Check for ringing, signal reflection, ground bounce, that sort of thing. I've seen all sorts of troubles caused by the sloppy "flying wires" that Xilinx provided with the cable. Illustrations:
**broken link removed**

Which 68 ohm resistors? If they are related to the Parallel Cable III, then that's strong evidence of a signal quality problem.

Are you using Master Serial mode, or JTAG mode? I see some references to both.

I've had problems with JTAG mode on various Xilinx FPGAs including Spartan-3. For reliable FPGA JTAG programming, I always power-cycle the FPGA board, or strobe PROG_B, before the JTAG download. If I don't do that, the download appears to work fine, but my FPGA logic may misbehave. The misbehavior depends on the previous FPGA configuration, so I think JTAG doesn't fully clear the FPGA. I can consistently repeat the problem on many different FPGA boards, including the Spartan-3 Starter Kit.

I've never seen a defective Xilinx FPGA. I've seen plenty of destroyed FPGAs, but those were our fault!

Be sure your PC board has good stiff power supplies and solid power/ground planes. Wobbly power can cause erratic FPGA troubles.

KO - like in boxing!
 

Hello again,

I don't see "Parallel Cable III" on Digilent's web page. Which cable do you have?

Where does your cable plug into the schematic? If it plugs into the box labeled "3.3V JTAG PROM", then iMPACT uses JTAG (aka Boundary Scan) mode to program the flash or FPGA, and the flash uses Master Serial mode to program the FPGA.

I don't see any VCC or ground pins on the (?) cable connector in the schematic.
 

echo47 said:
I don't see "Parallel Cable III" on Digilent's web page. Which cable do you have?
Click to expand...

OK - I have JTAG3 Cable. But i got a parallel III cable from Xilinx.

Now, i have experienced a weird behaviour. When JTAG3 Cable is powered with 2.5V, then Boundary scan works fine (but not with 3.3V).
With Parallel Cable III it needs to be powered at 3.3V for the boundary scan to work.

echo47 said:
Where does your cable plug into the schematic? If it plugs into the box labeled "3.3V JTAG PROM", then iMPACT uses JTAG (aka Boundary Scan) mode to program the flash or FPGA, and the flash uses Master Serial mode to program the FPGA.

I don't see any VCC or ground pins on the (?) cable connector in the schematic.
Click to expand...

Yes, my cable plugs to "3.3V JTAG PROM" box.
Do you mean i can not program directly the FPGA? (bypassing the flash)

I have added VCC (2.5V) and GND to the cable connector. It is not in the schematic.

BTW, echo47, thank you very much for all your help.
 

You found a combination that works fine? Great!

It still sounds like you have marginal JTAG signal quality (such as ringing or ground bounce) somewhere in the cable connection. If changing the cable, or a resistor, or a voltage, causes a dramatic change in the symptoms, then that's a big clue.

I have never used a JTAG3 cable or a Parallel Cable III, so I don't know their quirks. I use a Xilinx Parallel Cable IV. Here's a data sheet. Notice the "high performance ribbon cable". Xilinx switched to this cable to reduce customer headaches when talking to newer faster FPGAs.
**broken link removed**

3.3V on the JTAG signals is too much for the FPGA because VCCAUX is only 2.5V. However, those RSER resistors are probably intended to limit the current to a safe level, so maybe you are ok.

Your JTAG chain includes the flash and the FPGA, so you can use JTAG from iMPACT to burn the flash and/or configure the FPGA. If you power-up the board with no JTAG connection, the flash automatically configures the FPGA using Master Serial mode.
 

    S

    System.out

    Points: 2
    Helpful Answer Positive Rating
Thanks.

I have finally ensembled another board (just the FPGA without flash) and it success when programming. :D
 

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