When masters initiate transactions, how do they go to each slave in AXI interconnect?

hi all,
i'm currently designing amba axi interconnect with multiple masters and multiple slaves. When masters initiate transactions, how does it go to particular slave ? from the interconnect's point of view, how to decode it ? is it based on the address or by the transaction IDs?

Thanks.

difference between ahb and axi

If more than one master is using same slave, then decoding is done based on priority. from Interconnect point of view, if more than one acces to a same location is done simutaneously then it needs to resolve conflict and pass only one request.

interconnect axi

let me make myself clear. in amba axi, during a write transaction, master will assert the awvalid signal and slave will assert awready signal to say that its ready to accept the write transaction.

lets check this scenario. one master is asserting the awvalid signal, 2 slaves are asserting the awready signal. now, to provide the txn to the right slave, what decoding will be used ? will it use address provided by the master or the id of the transaction ?

In this scenario, there is no conflict from the master side, so, priority arbitration is not necessary from the interconnect.

difference between axi and ahb

"one master is asserting the awvalid signal, 2 slaves are asserting the awready signal. now, to provide the txn to the right slave, what decoding will be used ? will it use address provided by the master or the id of the transaction ? "


first AXI is a configurable interconnect, it all depends on how u configure,
Ist case
so all slaves can have seperate buses enrouted from the masters or a single master can have seperate interfaces such as AWvalid1 , AWvalid2, AWvalid3, ... etc. so now here in this case if a master's AWvalid (X) is high it looks for only AWready(x) to be high, it doesn't care even though AWready(x+1) is high.
IInd case
As you said in ur case if u have a single master signal and multiple slaves but a single interconnect then address decoding can be done. I don't think this will be feasible bcos AXI is made for high performance and the above scenario is similar to AHB Bus decoding.

But i don't believe the AXI Interconnect can be done this way, there is AMBA 3 Design Kit available from ARM where the configuration tool automatically develops the interconnect according to the options given(such as 3 masters 2 slaves .. etc)

Well if u r designing the interconnect with a single bus then there would be no use of using AXI in that SOC unless there are AXI Master/Slave interface IP's predefined and bcos of time consumption u develop the AXI interconnect. else AHB is directly suitable to ur case.

Thanks & Regards

difference between ahb and axi

i hope primecell interface (pl300 or pl301) applies to amba axi.

from the primecell interface, what i can infer is, each master is connected to the interface using a slave interface. so, if the master is going to have awvalid1 as signal, then, the corresponding interface of the interconnect will send the awvalid1 signal to the corresponding slave for which the txn is intended.

to send it to a corresponding slave, there will be a decoding, which i'm not sure how its done.

this is my understanding. is this correct ?

either this, or, if i've 4 masters and 5 slaves, each master will have a separate interface with each slave.(making it atleast 20 overall connections) in which case, i'm not sure what the interface is used for.

please correct me where i'm going wrong.

Added after 3 minutes:

One more question is, if there r separate channels, from each master to each slave, then, how is it possible to take care of atomic transactions, which involve multi-master writes ?

ahb axi difference

1) what i think is u need to design some kind of crossbar switch and priority
what u can do is insert some own extra ID fields /tags of interconnect so that slave can get idea about which master wants to read/ write
let say
master 1's id 2 wants to write on slave no. 2's id 3
so it interconect will see whether the bus is busy or not and depending on that it will send 1.2 wr_id to 2nd slave
since in case of single master slave only info avail is id.no.2
(see page 10 of axi specification.....In a multi master system the interconnect is responsible for appending additinal information to the ID tag to ensure that ID tags from all the masters are unique....id tag is similar to a master no. )

2) though it is written in axi specification there are imaginary 20 interfaces available (5*4)
what i think is there is no such direct path inside a interconnect u need to have some kinda switching funda that will provide access to the slave.....
there is difference between interface and interconnect..
interconnect is something like a device having slave part at master side and master part at the slave side interfaces...

i hope i am right ..if not plz inform...

differnce between a axi and ahb protocol

hi art_man,
u r right on both points. i agree with u that txns from different masters will be unique from the interconnects point of view. this is why we can have same txn id from different masters.

i agree with u that there should be some switching in the interconnect. this is my point exactly. how does it switch ? from the spec, i can think of two ways.

1. each slave can be assigned a range of txn ids that it can service. lets say that txn id is 4 bits long and to uniquify masters, lets add another 2 bits, for a max. of 4 master interconnect. irrespective of which master it comes from, removing the unique 2 id bits of the masters, will make the interconnect map the txn to a corresponding slave. in this case, the slaves just use the awaddr or araddr internally, and its not much of use to map the txns. this can be put to use in bridges, with axi interface on one side and some other interface on the other side and the address is just passed along.

2. the second option, which as eeeraghu pointed out, is to use the address itself to map to a corresponding slave, which is used in AHB.

i'm not clear of which decoding is used in AXI interconnects. as usual, let me know if i've made any mistakes anywhere.

what is the difference between axi and ahb ?

Hi,

Thanks for all ur inputs,

I have one point here, Interconnect has to decode with the address provided by the master interface, as the master interface will never know how many slaves are there in the architecture whereby it cannot issue different transaction ID's for different slaves, but it can issue different transactions using different ID's using different address.

if not the above case, if the interconnect can decode from tran_id's then master must know which slave it has to it drive the transactions. so the master interface must have decoded the address defining the slave.

Thanks & Regards
Raghu

amba axi interconnect

Hi Raghu,
i guess u r right. i came across sec 8.7 in axi spec, where use of IDs by interconnect is specified. it doesn't say anything about ID being used to choose slave.

Also, i suppose DECERR might not be possible, if ID is used for decoding. this point, i'm not too sure. correct me if i'm wrong.

axi interconnect ip

yes what raghu is saying is true.
I am not sure about points I made previously can be useful in interconnect but to unify each master's ID there is something written in AXI specs.
Address(or address range) can be used by interconnect for selecting the proper slave..as in the case of ahb..axi I think there is decode error provision and also 4k boundary limits the address decoder's size. Address decoding is very familiar technique used in many on chip as well as on board bus architectures.

Re: axi interconnect ip

You can download a free generic AXI master core from OpenCores.org
It has a configurable number of masters and slaves and such parameters.

Generic AXI interconnect fabric :: Overview :: OpenCores