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issue about 'define_name_rules' cmd of synthesis.

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quan228228

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define_name_rules

i want to restrict first character '\' on objects' name. Through I used following naming rule, the objects name still have first character '\'. Why? how to resovle it?

define_name_rules verilog -check_bus_indexing -allowed {a-z 0-9 _ []} \
-remove_internal_net_bus \
-flatten_multi_dimension_busses \
-first_restricted "\ _ 0-9"

Tks v m!

quan228228
 

how to use define_name_rules

try using -restricted {\} in the first command itself
 

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    quan228228

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flatten_multi_dimension_busses

nanda_kishore said:
try using -restricted {\} in the first command itself
Click to expand...

yes. This option can work. Thanks.

But, why does not option'-first_restricted' work well?


quan228228
 

define_name_rules sverilog

I think that -first_restricted will not go with the command "define_name_rules verilog".. I am not very sure with that... anyways.. try "define_name_rules verilog -help" for more options that goes with that command..
 

the DC report error:

we can not use argument 'restricted' with 'allowed' .

Anyway, eventhough i did not put '\' in allowed list, but the netlist still has net name has '\'. It is so strange.

Any reply welcome

quan228228
 

Hi,

May be you can use the two diffrent naming rule one with restrict option one with the allow options.first apply restrict rule and then allowed rules.after that if you write out the tool will remove the "\" from your design.

regards,
ramesh.s
 

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