Post and Pre Synthesis

Dear friends,

What is the basic diffrence b/w post and pre synthesis

also post and pre layout

I think you are talking about pre synthesis simulation and post synthesis simulation.. ..

pre synthesis simulation: simulation done according to the logic you have written.. only functionality
post synthesis simulation/gate level simulation: simulation done after synthesis considering each and every gate delays into account .. reports the violations in both functionality and timing. This also showas the mismatches you are likely to get due to wrong usage of operators and inference of latches..

Added after 19 minutes:

comming to post layout an dprelayout.. I assume you are talking about netlist..

pre layout netlist: This consists of the information of gate to gate connections according to the logic..

post layout netlist: This consists of the gate to gate and pin to pin connection of each gat eincluding buffers..just as it should go on the silicon die..