Altium Designer controlled impedance calculation is wrong

controlled impedance calculator

hi.

i just checked, the altium designer calculates trace widths for given impedances in a wrong way. very bad...
For a very unbalanced stripline, the error in width is about 200%.

it uses symmetrical stripline equations for assymmetrical striplines too. but that is totally wrong.

fortunately we can edit the equations, but i have no idea about the altium system variable names, but without it, its not possible to write a better equation.
Good equations can be found at:
**broken link removed**
but i have no idea how to translate the variable names for the protel.

so, does anyone have any ideas how to solve this?

Added after 19 minutes:

and also the Er can be different for an upper and a lower dielectric, so use some kind of average, like:
Er=(Er1*h2+Er2*h1)/(h1+h2)
or something similar.

ethernet routing impedance calculator

Altium doesn't claim that their impedance calculator will work for asymmetric striplines or differential striplines. The calculation done is a very simple one intended to get you in the ballpark for simple impedance situations. For the limitations on the calculation, see the middle of page 6 in "AP0107 Impedance-Controlled Routing.pdf".

For asymmetric striplines, or differential lines, you need to use a field solver (preferred) or one of the other calculators you can find on the web. A couple I can think of are: an Excel spreadsheet calculator that can be found at http://home.fnal.gov/~dcc/btev/Impedance Calculator.xls , or online at http://www.pcblibraries.com/resources/calculators/impAsymetricStripline.asp , or one that can be downloaded from http://www.ultracad.com/diff_calc.htm .

Once you have the results, you manually edit you trace widths to the proper values. You can use FSO (find similar objects) to do global edits.

If you want to see what is available for you to manipulate in the Altium Designer equations, open the impendance calculator from the stack manager. Click on "Helper" and then click on "Impedance" in the lower left window. The available variables are listed in the lower right panel. I believe you will find that you don't have enough flexibility to edit the Altium Desginer builtin calculator to give you the precision you are seeking. It's a fairly simple minded calculator at this point in its development.

controlled impedance differential pair

ok. thanx.

so i will calculate myself.
i am making an excell spreadsheet, to calculate few different trace's in the same time for few different materials. almost finished.


one more question:
for differential pairs, do you use minimum manufacturable trace separation?

ipc impedance calc

buenos said:

one more question:
for differential pairs, do you use minimum manufacturable trace separation?

Click to expand...

This question has a more complicated answer than might be apparent.

Most differential IC inputs and outputs are not true differential signals. Each side of the +/- signal is referenced to some common return within the chip. The circuit designer will terminate such lines with a resistor or capacitor to the appropriate reference plane. When laying out a PCB for such signals, you get better signal integrity and ease of layout by placing the two traces close together but not so close as to couple them tightly - generally separating them by 3-4x the height to the reference plane so as to uncouple them. This also makes routing easier since you can split the pair to get around a via or other obstruction without affecting the impedance seen by the pair. The differential impedance of such a layout would then simply be the sum of the impedance of each line as determined to the reference plane. The reason for placing them close together is to equalize the common mode "noise" from outside sources such that it cancels out. The reason for separating them 3h-4h is to keep each line uncoupled from the other.

A true differential pair, which has no internal common reference in the IC, must be routed as a tightly coupled pair. The closer you place one side of the pair to the other, the lower the differential impedance becomes for a given track width. Furthermore, to maintain the differential impedance, the pair must be kept at a constant spacing from beginning to end. This constant spacing requirement saves board space, but makes routing difficult because the pair has to be treated like one signal path over its entire length.

With that introduction, to answer your question, if you really want and need a true tightly coupled differential signal pair, you should look at what trace width is practical from your board routing. Once you have the width, you can use a field solver to find the required spacing. As the traces get closer together, the impedance decreases. As the width of the track decreases for a given separation, the impedance increases. If the spacing required to get the required impedance is too small for your fab, you'll have to change the width of your tracks and try again. The process is continued until you find a good balance between track width and spacing that can be fabricated. Keep in mind the practical aspects of tightly coupled traces - small spacing over a long distance is more likely to provide places to develop shorts; once you commit to this kind of coupling, you HAVE to keep it over the entire track length; available board space for routing has to be present to keep the coupled pair away from other pairs or aggressor traces to prevent cross-coupling.

If you would like to read more about the subject, check out:

**broken link removed**

http://www.sigcon.com/Pubs/news/5_2.htm

http://www.sigcon.com/Pubs/news/2_30.htm

**broken link removed**

altium designer impedance asymmetric stripline

why is bad if the signals are coupled in the pair?
i know, the Zdiff will be less than 2*Zse or Zse has to be bigger than Z0diff/2.
but is it bad? In intel appnotes, they advice things like this.

in a calculator page (see another topic by me) they adviced to use the thightest.


what is this:
"internal common reference in the IC"
A ground? Vtt?
if vtt then i think a DC is flowing into the same direction, and an AC is flowing into opposite direction, depending on the data. but i think DC currents have not much influence on signal integrity. or am i wrong?

i am calculating diffpair in 2 ways now:
-determine Z0se, and calculate separation
-use minimal manufacturable separation and calculate Z0se
(se=single ended)

is a field solver better than using equations?
i am making an excell spreadsheet with equations. with an excell i can spare a lot of time, because a field solver solves one trace and one structure at a time, but in excell i can calculate much more (i am doing 40 in the same time)

Added after 6 minutes:

in diffpairs, i am talking about: 100mbps ethernet, 480mbps USB, 400Mtps DDR memory reference clocks...
the "uncoupleness"-requirement is true for them too, or only for few Gbps pairs?

@ltium Designer controlled impedance calculation is wrong

if i calculated the differential impedance with 2 different imp.-calculators, and with given equations in excell, and the result was the same for symmetrical stripline at all of the methods.

then i used hyperlynx field solver-z0 planning, with the same parameters, the result vas about 25% different from the previous methods.

so, why the difference? the equations are some kind of IPC standard equations.

Re: Altium Designer controlled impedance calculation is wron

The difference between a field solver and simple formulae results from the fact that the formulae make assumptions about the geometry that aren't made by the field solver. A good field solver will take into account the fact that there is undercutting of the trace during etching - that trapezoidal shape to the track cross-section affects impedance. It will also take into account the thickness of the trace copper which causes the distance from the top of the trace to differ from the distance to the bottom of the trace. A field solver uses integral and differential equations to calculate the effects of the EM field around the conductor. A formula assumes a constant set of conditions for all conductors, and calcultes a result that is typical for many situations. In other words, the field solver does a more comprehensive analysis of the geometry than a simple formula does. Take a look at this article: **broken link removed**. Pay particular attention to Figure 2.

The reason to avoid tight coupling in the differential pair was explained in the references I listed to an earlier post. Once you commit to that geometry, you are locked into it for the ENTIRE length of the pair. If you need to separate the pair to enter the IC, or go around an obstacle, or to match lengths, you will need to adjust the track width to keep the impedance constant. It is just more difficult to route, and it is generally not necessary except to conserve space. The required close spacing also presents more opportunity for shorts, and makes manufacturing more difficult. Of course it can be done - but why do it if it isn't absolutely required?

The "internal common reference" in the IC I spoke of means that the chip design uses either the ground or a supply voltage as the other end of a terminating impedance for the signals on the differential legs. That means your differential signal is really two opposite signals, each referenced to one of the common voltage supply terminals (ground or VCC, VDD, etc). It has nothing to do with direct current flow, but rather what the REAL path is for each signal leg in the differential pair. Read the first reference I listed in my previous post.

@ltium Designer controlled impedance calculation is wrong

thanks for your answers.
you always know, what i want to know.

So i will use field solvers.
Is the hyperlynx accurate enough, or use something else, like SI8000?

For my excell thing, i think i will make my equations to be closer to simulation results of a field solver. This will not be used for final routing dimensions, but more accurate than the IPC equations, and good enough to help chosing the right PCB materials/stackup, which fits all my controlled impedance traces.

Re: Altium Designer controlled impedance calculation is wron

Both Hyperlynx and the Polar calculator have been shown to be accurate to within a percent or two. Either one should do the job well for you.

I suspect you already know this, but SI8000 is an Excel spreadsheet based field solver. Unfortunately, there's no way to see their underlying equations. It would be interesting to see what they have done to get the precision they have.

Re: Altium Designer controlled impedance calculation is wron

i want to make my own calculator, becose the if i gave board with 5 different Z0 and 3 different diffZ0, then if i want to try to change the dielectric (type of thickness) then i have to calculate separately, so many times to check, if its manufacturable, or not too big. i tried this, i spent 1-2 days, then i realized, that it would be good to have a tool, where i change the material, and it calculates all the rtaces for all the layers, if they are ok, or not.

i made it with the ipc equations.

i think i will spend this weekend to try to make it to be more accurate. i think there are 2 ways:
-modifying the ipc equations with constants, and simple exponential, or similar sub-equations, to make the results closer to the hyperlynx results.
-make simulation series with hyperlynx, and curve fitting. (maybe taylor series)

At first at one changing variable, then at another... maybe then at the first variable again... in an iteration. huge amounts of calculations, simulations.