shahzad ahmad
Junior Member level 1
plz tell how can i learn to lay down clock period constraint
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module top (clk, count);
input clk; // synthesis attribute PERIOD clk "50 MHz";
output reg [7:0] count=0;
always @ (posedge clk)
count <= count + 1;
endmodule
module top (clk, count);
(* PERIOD="50 MHz" *) input clk;
output reg [7:0] count=0;
always @ (posedge clk)
count <= count + 1;
endmodule
(* PERIOD="50 MHz",LOC="C5" *) input clk;