Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Please help me with my clock driver design

Status
Not open for further replies.
C

chemaphy

Junior Member level 2
Junior Member level 2
Joined
Oct 13, 2005
Messages
22
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,440
Hello all,

I am now designing a clock driver for a folding interpolation ADC. The output of the clock driver is connect to 32 comparators. The clock signal needs to be generated is 2GHz. Does anyone have experience with designing such a high speed clock driver??

Thanks for your help,
chemaphy
 

I think u should not connect clock driver output directly to i/p of 32 compatrators. B'cos the clock driver o/p cap. will increases. so use buffers between them.
 

    C

    chemaphy

    Points: 2
    Helpful Answer Positive Rating
satyasiva said:
I think u should not connect clock driver output directly to i/p of 32 compatrators. B'cos the clock driver o/p cap. will increases. so use buffers between them.
Click to expand...

Buffers are absolutely a must. Use cmos types.
 

You can use the clock tree format to drive the comparators.

But you need to carefully take care the layout matching issue.

It will affect your dynamic performance in such high frequency.

Usually, the inverter size is like 1-->3-->9.

Yiibn.
 

    C

    chemaphy

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top