Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The gain required and the UGB should be directly related to the PSRR required for your BGR.IF the supply voltage has high freq noise and noise amplitude is more , then you need UGB high.PSRR is the inverse function of the loop ghain curve.Also the high freq. PSRR can be achieved by adding capacitors to the circuits at appropriate places.The loop need not work for controlling / rejecting all the high freq. noise.... typically 40dB PSRR is good enough for BGR even for high noisy power supply DRAM's......... something like 100mV P-P noise on supply...... If you need the BGR for power supervisory chips, then you can gave high gain and low bandwidth.
Regards.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
