Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to determine setup time for a flop?

Status
Not open for further replies.
G

giri_lp

Member level 3
Member level 3
Joined
Feb 11, 2006
Messages
61
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,657
fixing set-up time

How to determine setup time for a flop? Is it technology dependent?
 

fixing set-up time

you can refer to the documents about standard cell libs!
 

Re: fixing set-up time

Hi Giri_lp,

It is process dependent. Basically it is a circuit levle property for a flop and depends upon Process Volatage temperature and also it's topology.

I hope this helped
:D
 

Re: fixing set-up time

Hi
can you be more specific/or just tell me the like where i can get documents for the standard cell...


Regards,
Giri
 

Re: fixing set-up time

**broken link removed** gives a case study for different topologies
 

    G

    giri_lp

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top