What should I prepare for the coverage estimation if I have insert scan chains?

hi all

i have insert scan chains in my design.and what should i prepare for the coverage estimation? and the dft drc check is ok.

thanks

test_simulation_library

You can use TetraMax for this.

help me

You can use command -- estimate_coverage in DFT compiler.

help me

I used Tetra max a long time ago and it was a total failure

help me

A total failure?! why?

Does DFT C can deal with the coverage estimation completly?
now i encountered a problem when i use estimate_test_coverage,and the log infos show that u should set_test_simulation_library first. i dont know what library it means? where can i get it?

anyone can show me the detailed procedure for this problem?
i am an newer, thanks everybody!

Re: help me

The test_simulation_library is the verilog library used by DFTC or TetraMAX (which, if you have it, is the preferable way to get your fault coverage) to model your circuit. Could be standard cell libraries, for example.

If you have DFTC, consult the doc tree for the best procedure. I think it varies according to version - for example, I think the command 'estimate_test_coverage' is deprecated in XG mode.

Hope that helps,
John
DFT Digest

help me

hi dft_guy

where can i get the test_simulation_library? Standard cell libraries shouldn't a verilog lib.
Am i right?

By the way , what does the doc tree means?

Really appreciate for ur kind help~

Re: help me

Don't get confused between a Synopsys library, as in '.lib', and a verilog library (which is normally used for simulation, and is a '.v' file containing a module for each cell in the library).

In most ASIC library situations, you'll have multiple parallel directories where your tools read different views of the library: there's a synth view, a sim view, a layout view, ATPG view (for ATPG tools that need a special library) etc.

TetraMAX reads the verilog library (sim view, if you will), except in the case of embedded memories, where the 'verilog' syntax is very limited - that's another subject.

What I mean by the doc tree is the sub-directory of the installation directory where the documentation is held. The location will vary from site to site - consult the guy who installs/maintains your EDA tools.

John
DFT Digest