How to fix setup violation occurring after chip completion?

how setup violation is removed

Hi,
If setup violation occur after completion of chip,then to fix that what we need to do.

Re: setup violation

Hi,
reduce clock frequency , by this way ur design performance will decrease but u don't need to modified ur design else u need to modified ur design.
Regards
udit

Re: setup violation

hi,
Setup violation results because the data didnot arrive setup time before the active clock edge:
so ,Let's analyse the reasons for this ,the data didnot arrive before the specified time because there has been a significant delay in data path.If you analyse the timing report you find the because of the added buffers in combi logic path,we get a delay.
These buffers are needed for increasing the drive strength of thesignal .So according to the reasons stated above ,we come to conclusion the buffers can't be removed .But you have to fix setup violation.
We have 2 options now:
1).Decresing frequency so that you give an additional cycle for data to reach ,so that there is no setup violation.But our promise of design which would run at particular frequency would fail.so we abondon the approach.

2).Going back to discussion in the 1st paragraph we need to upsize the buffer ,which would result in buffer being replace with a footprint ,with decreased delay and high drive strength .
This is how we fix setup violations.

Re: setup violation

Actually, If a chip has setup violations, it is not considered as COMPLETED.
A completed chip cannot have any violations.

To Decrease the setup violations,
Insert the buffers. As delay is proportional to the square of the length of the net, inserting the buffers will decrease the length, thereby decreasing the delay.So, better insert buffers in the middle of the net.

Also, U can upsize the standard cells used in the design. For example ANDX1 can be upsized to ANDX4 or more. But this doesnot guarantee the result as netdealy may increase.

setup violation

Insert a high drive strength buffer in the failing path!
Sumit

setup violation

Hi All,

once the chip was manifactured we can avoid setup violation only decrecing the frequency.

regards,
ramesh.s

Re: setup violation

Thanks all,but somebody told me other solution for this query,i.e by varying pvt conditions.I want to confirm is it rigt way to fix.If yes please explain the reason.

Re: setup violation

designer_ec said:

Hi,
If setup violation occur after completion of chip,then to fix that what we need to do.

Click to expand...

What stage is the chip in.
u said complettion of chip, means after RTL, or GDSII.

Re: setup violation

hi ,
setup violation should not be fixed by varying PvT conditions as would fail the promise of chip working at alll conditions.
Regards

Re: setup violation

Hi,

Setup violations can be fixed by decreasing the delay of the concerned net. This can be done either by upsizing the driving buffers or if the net length is too large than by adding the extra buffers. In both the cases any design change ripples back to the whole design and some more changes may also be required to be made. If the net delay is caused by the cross talk delay then we have to see the adjacent net driving strengths also and adjust the driving dtrengths accordingly.