Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

setup and hold calculation in latch based design

Status
Not open for further replies.

designer_ec

Member level 4
Member level 4
Joined
Mar 31, 2007
Messages
68
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
1,752
Please anybody describe how to calculate the setup time and hold time in latch based designs.How differentiate this setup and hold time calculation with respective to flops and clock gating.
 

Hi
setup time and hold time calculation is same as in flip flop but in case of clock gating it will different..
suppose there is single flip flop and u r doing clock gating(some combinational logic is added at input of F/F ) then Global setup time will increase and Global hold time will decrease ..
Regards
 
Hi uditkumar ,
Thanks for your solution,but I need elobaratly about setup and hold calculation in those three cases.If you have any meterial regarding these topics please send to my
mail ID.which is designer_ec@sify.com.Other wise share in this forum,then useful for other peoples also.And also let me know that what is the difference between global setup,hold and normal setup,hold.
 

Hi,
you can find one pdf at


Regards
udit

Added after 12 minutes:

Hi ,
u can find some more material


regards
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top