Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What is the max. allowed values of R, L, and C on chip??

Status
Not open for further replies.

knack

Member level 2
Member level 2
Joined
Feb 25, 2007
Messages
48
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
Austria
Activity points
1,674
Hi,

In design of a complete PLL on chip using 130nm technology, what's the maximum/minum allowed values of on-chip resistors, capacitors, and inductors (R,C, and L)..

Also, is there some tricky ways to override these values (e.g. MOS resistor and capacitor rather than poly R and MIM cap. ...etc.)

Thank you :)
--Knack
 

Also, is there some tricky ways to override these values (e.g. MOS resistor and capacitor rather than poly R and MIM cap. ...etc.)
MOS cap can be used in the LPF section, and resistors should use poly type (cause it has lower value of Voltage coefficient (VC)) and usually the resistor area is small as compared to MOS cap., so there is no need to replace it with MOS resistor.
 

    knack

    Points: 2
    Helpful Answer Positive Rating
Max. RLC depends on the loop equations to provide enough phase margin. Other than that, all other parameters are minimal importance.
You can of coz choose to select MOS resistor and capacitor, however, just the variation would be quite large and you need to leave margin for design only.
 

    knack

    Points: 2
    Helpful Answer Positive Rating
FThank you all,
But it seems that you still didn't get what i want to know..
From your replies, if i don't know, i may go to use a 1µF on Chip cap and 1MΩ resistor!!!!!!!!!!
I want numeric typical values :D

Thanks
Cheers,
-- Knack
 

First off I assume you mean low frequencies or @ DC. Things can change drastically at high frequencies.

Secondly you should go to your 130nm Design Manual and look up what types of passives are allowed for your process. (MiM, VNcaps, NFETcaps; just to name a few types of capacitors). The design manual will give you equations for how to calculate the value of your passive element as a function of area.

Next figure out how much area you can waste on passive elements. If you want to take make your whole chip into a giant inductor go for it. Ask Intel to make you a 45nm, 12 inch wafer cap!!

Thus we can't tell you what the max sizes are, its all about trades offs.

Here are some rules of thumb:
1nF is really large for caps
10kohms or less for resistors
10nH for inductors

Next thing to consider is that just about any passive can be faked (crappy faked) with transistor. Long channel length transistors for Mega-ohms resistors, inductor being replaced with transistors in tank oscillators, and lots more tricks.

Cheers,
Hemlock
 

    knack

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top