Looking for materials regarding floorplanning

sree205 said:

Please go through the floorplanning and the general physical design flow in ASIC by john sebastian smith. It ll give you explanation from starter's perspective. after that its tool documents that you will be relying on. all the best !!

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sree205 said:

if u have access to the tool, u can learn the basic flow from this tutorial

h**p://discovery.bits-pilani.ac.in/discipline/eee/agupta/advanced-vlsi/LAB/ganesh/labs/lab2.htm

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roy_ece said:

The files for floor planning depends on the type of design that you are presently
working on i.e., a partitioned design (or) a full_chip design .
If your working on cadence tools ,the files may be as following for partioned design :

1.verilog netlist (or) RTL netlist file(s).
2.Timing Library files for Worst case ,Best case analysis.(known as .lib)
3.Physical library files for info regarding placement and Routing (known as LEF).
4.Timing constraints file(s).

For Full chip along with the above files you require additional file about IO pads
i.e.,e IO Assignment file.

Before Floor planning we,
Specifying FloorPlan :In this we give core and die sizes.

The Types floorPlanning are:

1).Automatic Floor Planning: in this the tool does the floor plan of modules and macros automatically.
2).Relative floor plan:In this we place macro and place other macros relatively to this location of macros ,soft modules are placed automatically by tool.

For more detailed Understanding you need to take a course on Cadence flows.

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