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Recognizing of a bit-stream that is divisible by 5

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bits stream divide by 5

Hi,

I want to be able to recognize whether a bit-stream (size not specified) is divisible or not divisible by 5. The incoming bits are appending to the LSB side of the already stored bits. The algorithm should work even on an infinite stream of bits.

THANKS IN ADVANCE
 

divide by 5 bits question

The number which is diviable by 5 must be xxxx0d or xxxx5d. That's to say, you can check the last received three bits to find out whether the bits are 000b or 101b.
 

is 5 divisible by 908

@ staraimm
I think that doesn't work this way in binary systems(what about 1111b).

Well one has to use a state machine (moore will be simpler to use). Try making one for divide by three(to understand the concept) and try for divide by 5 on similar lines.

Regards
tronix
 

This is second time I see the question posted here! The answer is simple
what we need to track is the LSD of equivalent BCD no as we shift in the
bianary no. if BCD is 0 or 5 the bianary no. is divisible by 5.
Here is the verilog code...
Code: 
 module divisible_by_5(
   // Outputs
   div_by_5, 
   // Inputs
   clk, reset_n, sin
   );
   input clk, reset_n;
   input sin;
   output      div_by_5;

   reg [4:0]   bcd_eq, bcd_eq_nx; //bcd equivalent lower digit of the no.

   assign      div_by_5 = (bcd_eq[3:0] == 0) | (bcd_eq[3:0] == 5);
   
   always @(posedge clk or negedge reset_n) begin
      if (!reset_n) begin
         bcd_eq <= 0;
      end else begin
         bcd_eq <= bcd_eq_nx;
      end
   end
   
   always @(bcd_eq or sin) begin
      bcd_eq_nx = {bcd_eq[3:0], sin};
      if (bcd_eq[3] | (bcd_eq[2] & (bcd_eq[1] | bcd_eq[0])))
        bcd_eq_nx = {bcd_eq[3:0], sin} + 6;
   end   
endmodule // divisible_by_5
 
hi,
Well, the following code attach above is not appropiate for infinite bit-stream.this might work on software language anywayz the simple solution of your question is that think in term of remainder if the value is divisible by 5 ,then the possible remainder are 0,1,2,3,4 so there are five state , now try to develop the FSM in which states i.e S0,S1 represent a remainder not a value
I hope my answer will help you.
Naail
 
can someone explain this problem by a state diagram...
 

orangelogic said:
can someone explain this problem by a state diagram...
Click to expand...

Two rules:
1. when '0' come then current value will multiplied by TWO.
2. when '1' come then current value will multiplied by TWO plus ONE.

Current '0' '1'
Value come come
------------------------------------
10(0) 20(0) 21(1)
11(1) 22(2) 23(3)
12(2) 24(4) 25(0)
13(3) 26(1) 27(2)
14(4) 28(3) 29(4)


the value in (#) is the reminder.
now
supposed each (#) as a state
then you already have FSM.

Khalil
 
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