manofwax
Junior Member level 1
vernier interpolation
Dear All,
I'm working on a project about time interval counter using vernier interpolation principle to get a higher resolution. If you are not family with vernier interpolation, it's totally fine, coz my question is quite general.
Here's my problem:
Input: Clk_ref with 100MHz
Input: Start_trigger
Output: Clk1 with 100MHz * (16/17) when the Start trigger signal goes high
I'm using virtex 4, I can easily get the output frequency with the DCM in FPGA. This is what I did. I fed the input clk_ref to the DCM and then I would get the output with the frequency that I want.
However, I don't want the output freq to be generated right away. I want it to happen AT THE MOMENT Start_trigger signal goes high.
Feeding the Clk1 and Start_trigger into an AND gate isn't an solution. Because the output of the AND gate will not go high at the moment(with some delay) Start_trigger go high. The output of the AND will just wait till Clk1 goes high.
This is what i want:
Clk_ref:xxxxxxxxxx|____|-----|____|-----|____|-----|____|-----|____|
Start_trigger:xxxxxx__________________|------------------------------------
Clk1:xxxxxxxxxxxxxx__________________|-------|_____|------|_____|------
Summary:
* freq of Clk1 = freq of Clk_ref * (16/17) <--- I can do this with DCM
* Clk1 will be triggered by Start_trigger;
Thanks in advance. Any suggestion and idea will be appreciated!!! Thanks.
Dear All,
I'm working on a project about time interval counter using vernier interpolation principle to get a higher resolution. If you are not family with vernier interpolation, it's totally fine, coz my question is quite general.
Here's my problem:
Input: Clk_ref with 100MHz
Input: Start_trigger
Output: Clk1 with 100MHz * (16/17) when the Start trigger signal goes high
I'm using virtex 4, I can easily get the output frequency with the DCM in FPGA. This is what I did. I fed the input clk_ref to the DCM and then I would get the output with the frequency that I want.
However, I don't want the output freq to be generated right away. I want it to happen AT THE MOMENT Start_trigger signal goes high.
Feeding the Clk1 and Start_trigger into an AND gate isn't an solution. Because the output of the AND gate will not go high at the moment(with some delay) Start_trigger go high. The output of the AND will just wait till Clk1 goes high.
This is what i want:
Clk_ref:xxxxxxxxxx|____|-----|____|-----|____|-----|____|-----|____|
Start_trigger:xxxxxx__________________|------------------------------------
Clk1:xxxxxxxxxxxxxx__________________|-------|_____|------|_____|------
Summary:
* freq of Clk1 = freq of Clk_ref * (16/17) <--- I can do this with DCM
* Clk1 will be triggered by Start_trigger;
Thanks in advance. Any suggestion and idea will be appreciated!!! Thanks.