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Do you think that the slow input clock may affect my lock detection counter?

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crazy_analog

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Hi,

I am running the PLL full chip simulation and i spent almost 2 weeks (simulation time is over 12ms), but i could not see the lock signal until today.
My PLL input clock speed is very low frquency such as few ten KHz speed.
Do you think that the slow input clock may affect my lock detection counter?
My lock detection counter is 5 bit counter.
Can you help me out? I need to your help.

Thanks
:D
 

Re: PLL input clock

To ensure stability, good spur attenuation and linear behavior, the loop bandwidth of the PLL should be = fref/10 .So, if you ensure that and for very low reference frequency, your loop bandwidth would be extremely small, leading to a very large settling time .So, you should ensure first thst your PLL is stable, then you should try to increase the reference frequency for faster settling .You can increase the reference frequency without being constrained with the frequency step by using fractional-N architecture .
 
PLL input clock

Hi Crazy_analog

If your input frequency is such a low frequency, then your lock is ridiculous.
If under your application, if u really need to use that, I prefer you add a cascade of frequency doubler to increase the reference frequency to increase the lock time.
 

PLL input clock

You should use the behavior model.
 

PLL input clock

Try to use HSIM. Define analog block such as loop filter as analog and others as digital, then it will be at least 100 times faster than spice.
 

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