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How to implement a pll using fpga?

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eelinker

eelinker

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How to implement a pll using fpga?
 

pll fpga

Do you mean implement PLL using verilog code?!


I dun understand why you wanna implment PLL. In Virtex 5, you can simple instantiate the PLL and use it. It's easy if you read all document.


Bear in mind PLL has analog circuitry inside. I dun think we can design it in FPGA. We should the the coregen.

Thanks.
 

    eelinker

    eelinker

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xilinx pll

Hi,
Many of the FPGA families are comming with with PLLs or DCM (Digital clock managers). Example stratix-II, Vertix-II have them. You need to write a wrapper around these to make it cmatible with your PLL. However they offer limited functionality as compaired with analog PLLs in ASIC. DCMs doesnt give options to change the multiplier & divider in RUN time. You need to fix them during synthesis.

I dont think that if you have any analog pll module, that you will be able to put in FPGA as it is.
Hope this will help you.

Best luck,
Ram
 

    eelinker

    eelinker

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digital pll fpga

I feel its not possible to implement a PLL in FPGA(with out any special units like DCM). do you have come across any ckt(digital) using combinational or sequential logic which can give more frequency signal than the clock we are feeding? in your studies or work?
 

    eelinker

    eelinker

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pll xilinx

What device are you using? Why do u want to implement pll? Hm... in xilinx, u can using the core gen to generate dll/dcm. Hope this helps.
 

    eelinker

    eelinker

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fpga pll

u need to use coregen for using the pll inside an fpga....i don't think u can write any verilog/vhdl code for it...
 

    eelinker

    eelinker

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pll on fpga

What's coregen?
Is it possible to use it's implemented pll in a fpga based modem?
What's the frequency characteristics of fpga?

Thanks
 

pll+fpga

I think that you can write a one but you should
1- design its parameters
2-convert each analog block to its digital equivelant (PD=mult,LBF=IIR,VCO=NCO) and so on
 

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