rambus_ddr
Advanced Member level 4
veriloga opamp
I show a opamp example, but i have some question about their meaning.
what vout are the output of this opamp. let's us discuss their meanings.
The following is the main part of verilog-a code
1 @(initial_step or initial_step("dc") ) begin
2 cl= iin_max/(slew_rate);
3 gm_nom=2*'pi*freq_unitygain*cl;
4 r1=gain/gm_nom;
5 vmax_in=iin_max/gm_nom;
6 end
7 vin_val=v(vin_p,vin_n) + vin_offset;
8 // Gm stage with slewing
9 I(vref,cout) <+ V(vref,cout)/100e6;
10 if(vin_val > vmax_in)
11 I(vref,cout) <+ iin_max;
12 else if (vin_val <-vmax_in)
13 I(vref,cout) <+ -iin_max;
14 else
15 I(vref,cout) <+ gm_nom*vin_val;
16 //dominant pole
17 I(cout,vref) <+ ddt(cl*v(cout,vref));
18 I(cout,vref) <+ v(cout,vref)/r1;
19 //output stage
20 I(vref,vout) <+ V(cout,vref)/rout;
21 I(vout,vref) <+ V(vout,vref)/rout;
22 //soft output limiting
23 if (V(vout) >vsupply -vsoft))
24 I(cout,vref) <+ gm_nom*(V(vout,vspply_p) + vsoft);
25 else if (V(vout) <vsoft))
26 I(cout,vref) <+ gm_nom*vsoft;
27 end
I show a opamp example, but i have some question about their meaning.
what vout are the output of this opamp. let's us discuss their meanings.
The following is the main part of verilog-a code
1 @(initial_step or initial_step("dc") ) begin
2 cl= iin_max/(slew_rate);
3 gm_nom=2*'pi*freq_unitygain*cl;
4 r1=gain/gm_nom;
5 vmax_in=iin_max/gm_nom;
6 end
7 vin_val=v(vin_p,vin_n) + vin_offset;
8 // Gm stage with slewing
9 I(vref,cout) <+ V(vref,cout)/100e6;
10 if(vin_val > vmax_in)
11 I(vref,cout) <+ iin_max;
12 else if (vin_val <-vmax_in)
13 I(vref,cout) <+ -iin_max;
14 else
15 I(vref,cout) <+ gm_nom*vin_val;
16 //dominant pole
17 I(cout,vref) <+ ddt(cl*v(cout,vref));
18 I(cout,vref) <+ v(cout,vref)/r1;
19 //output stage
20 I(vref,vout) <+ V(cout,vref)/rout;
21 I(vout,vref) <+ V(vout,vref)/rout;
22 //soft output limiting
23 if (V(vout) >vsupply -vsoft))
24 I(cout,vref) <+ gm_nom*(V(vout,vspply_p) + vsoft);
25 else if (V(vout) <vsoft))
26 I(cout,vref) <+ gm_nom*vsoft;
27 end