question about slow.lib and fast.lib on Design Compiler

180nm cell library for design compiler

When we synthesis a design with Design compiler, if we need to synthesis it with both slow.lib and fast.lib ? but maybe different library with the different synthesis result . of course ,typical.lib too ?

slow.lib

SLOW, FAST and TYPICAL synthesis libraries are provided for timing based synthesis.

The SLOW lib is used for Hold time and the FAST lib is used for Setup time checks. Thus for synthesis we have to use these 3 libraries so that the compiler can perform a timing-based synthesis and give us timing reports on setup and hold times.

what is slow , fast and typical corners in timing

but when u synthesis a design with slow.lib,you get some standard cell from this slow.lib different with fast.lib .so you will get different gate netlist. which gate-level netlist do we ought to select ? although the gate-level netlist meet timing from slow.lib,it dont means it will meet timing from fast.lib

hold check slow corner

I havent used Synopsys tools, but in Cadence SoC, you need to provide all the libraries. This includes the Standard-cell libraries, timing libraries and capacitance libraries.

Other than the fast, slow and typical libs, you also should have the standard cell library. All these are inputs to the synthesis and P&R tool. The fast, slow and typical libraries are only used to check for timing and not entirely for synthesis. They contain the same cells but with different timing parameters for setup and hold time calculation. The tool will use the standard-cell library file you provide to synthesize the library. Typically you should have a 90nm or 180nm std-cell library such as tp90gphc.lib or somethin (i dont remember the file name) in your library folder. This is the std-cell library.

slow lib

but, slow.lib ,typical.lib,fast.lib include standard library,when synthesis with Design Compiler .only need to set target_library slow.lib or tyical,fast.If you set target_library slow.lib,then...Design Compiler select some standard cell from slow.lib according to not only function ,but timing information . timing information from slow.lib is different from fast.lib. when Design Compiler select a cell from slow.lib according cell's timing information for meeting setup/hold demand.but Design Complier select not the same cell from fast.lib according fast library timing infomation.That means gate-level netlist from slow.lib maybe is different from fast.lib .although cell name in slow.lib is the same as cell name in fast.lib.but cell name in gate-level netlist from slow.lib is not the same as cell name from fast.lib.

fast slow lib model

Hi All,

hear is the complete answer for libray selection and why we need to selct that library.
Q1) which library we need to use for synthesis and why?

ANS:-
we need to synthesize the RTL with the slow.lib since In the slow library all the delays are calculated according to the worst case corner.
so the delay caused at this point is high compared to the remaining corners.
but the cell design is same for all the corners.

the compiler will use the slow.lib is for the SETUP time corner and fast.lib is for the HOLD time calculations.

Q2) why the netlist is diffre when we synthesis with the SLOW.lib and FAST.lib?
ANS:-
in any compiler the tool will follow the optimisation in the following priority way
1.timing of the design.
2.area of the design.

when the tool is doing the synthesis with the FAST.lib where the delays are less the tool will map the design with the less drive strength cell(min area since it don't have extra amplifier compared to the high strength cell).so you may expect the cell with X1 drive strength instred of cell with X2 drive strength.in this manner u may expect the diffrence in the netlist but if u compare the netlist in the formal verification tool it will report's u that there is no miss match is present in both the netlist.

when u do the syntheis with the fast.lib you may see the hold time problems which are not present when u do the synthesis with teh slow.lib.


regards,
ramesh.s

hi,rameshsuthapalli
Thanks firstly,
1.u mean that we ought to synthesis a design with slow.lib.not care typical and fast.lib more .Just slow.lib is WORST condition.
2.u mean that we will get the same result when synthesis with slow.lib and fast.lib ? although maybe select the different standard cell with slow.lib and fast.lib,of course function is the same ,but gate-level netlist will be different

Hi ,

yes,u have to do the synthesis with the slow.lib.

regards,
ramesh.s

I think you should synthesis you design with both. The SDF should have both worst and best case timing in it. To do the sta, you just select which you will use for setup or hold check.

The design timing and setup time will be checked by slow and hold time by fast. There is as such no use of typ
Sumit

hi ramesh,

thanks for ur valuable points.but am bit confused.kindly help me.
am using rtl compiler(cadence).
fine as u said logic synthesis is performed using slow.lib w.r.t setup.

1] for the same RTL synthesys am checking setup(using slow.lib) and hold(using fast.lib).
as the cell delay differs in both .lib i will be getting different hardware eventhough my functionality is same.
so ,
for the hardware which we are checking for setup we will not check hold.
for the hardware which we are checking for hold we will not check setup.

finally which design will be given to the nextlevel(eg:socencounter).

2]moreover here in rtl compiler(logic synthesys part) am dealing with only setup time.so when i will set my fast.lib

dont mind if my question is not worthful.