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How to estimate the required buffring for a clock after place and route?

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alzomor

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Hi

Is it possible to do Clock tree synthesis "CTS" for vertix-4 FPGA using Xilinx ISE ?
And if possible How to do it?

How to estimate the required buffring for a clock after place and route?

Salam
Hossam Alzomor
www.i-g.com
 

Re: Clock tree synthesis

alzomor said:
Hi

Is it possible to do Clock tree synthesis "CTS" for vertix-4 FPGA using Xilinx ISE ?
And if possible How to do it?

How to estimate the required buffring for a clock after place and route?

Salam
Hossam Alzomor
www.i-g.com
Click to expand...

In case of FPGA you can not do CTS, It is purely an ASIC part. Clock Routing resources are already available inside the FPGA. However You can select the low skew lines for your clock signal while doing synthesis with ISE. Low skew lines are specifically provided in the FPGA fabric for clock and other critical signals.

Salam
 

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    alzomor

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