How to intialize a RAM(VHDL)

vhdl initialize ram zero others

Hi..I need some guideance on writing VHDL code for a RAM..Currently i have wrote a VHDL code for a RAM Which the initial value of all the adrees are '0' when Read operation occurs...I want to create a Ram which i can intialiaze the values in the addresses according to my usage..Can someone help me with this? Here i past my VHDL code for my RAM(Initial vaues are zero)..Can someone show me how to write the code to initialize a RAM???Thank u!!!

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ram IS
GENERIC
( ADDRESS_WIDTH : integer := 4;
DATA_WIDTH : integer := 8);
PORT( clock : IN std_logic;
data : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
write_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
read_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
we : IN std_logic;
q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0));
END ram;

ARCHITECTURE rtl OF ram IS
TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
SIGNAL ram_block : RAM;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(to_integer(unsigned(write_address))) <= data;
END IF;
q <= ram_block(to_integer(unsigned(read_address)));
END IF;
END PROCESS;
END rtl;

initialize ram vhdl

Hi
u can write a for loop to initialize ur ram as per ur requirement. say for eg... when there is a reset u initialize to to 0 the same ways u can initialize to you values after reset and then start using it.....

but for that u need to have all the values u want to initialize into the ram....

reset ram vhdl

signal mem_blobk : RAM := (others => (others => '0'));

initialo value in vhdl ram

bansalr said:

signal mem_blobk : RAM := (others => (others => '0'));

Click to expand...

This is not true .. this resets the contents of the memory, not the address .. SivabalanBalasundram was asking about how to initialize the address ..


For SivabalanBalasundram , if you want to initialize the memory address with whatever you want whenever you want , simply provide an input to the module you have expressing this address .. and once you enable the module for example, that input is mapped to the memory address line ..

vhdl sram initial value

use Core gen from Xilinx or Wizzard from Altera (depends which platform you are using) to create memories, those wizzard will allow you to inint memoris


regards

s3034585 said:

Hi
u can write a for loop to initialize ur ram as per ur requirement. say for eg... when there is a reset u initialize to to 0 the same ways u can initialize to you values after reset and then start using it.....

but for that u need to have all the values u want to initialize into the ram....

Click to expand...

Actually..I have already done that but i had problems when i want to compile the code because my memory size s 4096 bytes i m creating a memory which my data are stored in 128 bits per address . The address using 8 bits(256 location) which gives me a memory which can store 4096 bytes... can u help me in other ways like .mif file or any other...

SivabalanBalasundram said:

s3034585 said:

Hi
u can write a for loop to initialize ur ram as per ur requirement. say for eg... when there is a reset u initialize to to 0 the same ways u can initialize to you values after reset and then start using it.....

but for that u need to have all the values u want to initialize into the ram....

Click to expand...

Actually..I have already done that but i had problems when i want to compile the code because my memory size s 4096 bytes i m creating a memory which my data are stored in 128 bits per address . The address using 8 bits(256 location) which gives me a memory which can store 4096 bytes... can u help me in other ways like .mif file or any other...

Click to expand...

If you are modeling memory in order to later on use a similar one with your synthesized RTL, then you need to check if there is a memory module supplied by your memory compiler similar to that one you have modeled ..

I myself never dealt with any memory module with a width of 128-bit !!!