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What library should I use when I synthesize a design?

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dannyic

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what library I should use when I synthesize the design, slow.lib or fast.lib?
Thanks. Is there any rule?
 

Synthesis lib

Hi all,

use the slow.lib for the synthesis with the 25% timign margin on each clock will give better results.

regards,
ramesh.s
 

Synthesis lib

you want to make sure that your chip work in the worst conditions (typically 125C, 10% voltage drop and bad parasitic) so in synthesis you must use these conditions plus some margins... 25% maybe is quite for a margin..
 

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    dannyic

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Synthesis lib

Thanks. Is that meaning if I run STA like prime time and I get worse case timing violation for example 130 ps (clock is 4 ns), it is still ok according to your comment because there is 25% margin. is this correct?
 

Re: Synthesis lib

no it is not ok.

You should define your clocks with the margin so in the end you don't get any violations.
The margins are to be extra safe not as extra tolerance to errors.

If you are designing at .13 or .09 then you should also consider OCV and SI effects... but that is another story
 

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    dannyic

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Synthesis lib

25% is a lot of margin, even for .09 and even with on chip variation effects (which start to appear at .18 for some processes, btw).
 

Synthesis lib

for 25% margin, does that mean the clk should be 3ns with the worst case if the spec of clk is 4ns.
 

Synthesis lib

25% is quite a lot.

if your clock is 4ns (250MHz) you should have 10-15% margin plus your clock jitter. You can find the clock jitter from your pll specification if it comes from a PLL.

After PnR when you have exact clock skew information you can probably lower your margins on the final sign-off STA
 

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    dannyic

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Synthesis lib

25% is used in syn or sta?
how can i create a clk with 25% timing margin, "period" or "uncertainty"?
thanks a lot.

Added after 9 minutes:

There is another question.
If there are a few clocks from the same pll and they have different periods, such as 83.3ns, 16.6ns, 33.3ns, how can I create the "margin"?
method 1:
define the period : 83.3*75%, 16.6*75%, 33.3*75%
method 2 :
define the period : 83.3-C, 16.6-C, 33.3-C, C is a fixed value

thanks a lot
 

Re: Synthesis lib

Thinkie said:
25% is quite a lot.

if your clock is 4ns (250MHz) you should have 10-15% margin plus your clock jitter. You can find the clock jitter from your pll specification if it comes from a PLL.

After PnR when you have exact clock skew information you can probably lower your margins on the final sign-off STA
Click to expand...

how do you define the clock with 10-15% margin? is it defined as 3.8 ns or 4.2 ns? please advise! Thanks.
 

Re: Synthesis lib

dannyic said:
Thinkie said:
25% is quite a lot.

if your clock is 4ns (250MHz) you should have 10-15% margin plus your clock jitter. You can find the clock jitter from your pll specification if it comes from a PLL.

After PnR when you have exact clock skew information you can probably lower your margins on the final sign-off STA
Click to expand...

how do you define the clock with 10-15% margin? is it defined as 3.8 ns or 4.2 ns? please advise! Thanks.
Click to expand...

anyone can help this out.
 

Synthesis lib

please look up set_clock_uncertainty command in DC
 

Synthesis lib

If you use the clock_uncertainty you should not have it for hold times too as you will get a design full of buffers that you don't really need.

You can use a different value of certainty of hold and different of setup times
 

Re: Synthesis lib

Thinkie said:
If you use the clock_uncertainty you should not have it for hold times too as you will get a design full of buffers that you don't really need.

You can use a different value of certainty of hold and different of setup times
Click to expand...

I think set_clock_uncertainty is used during prelayout stage. For post layout, I am using "set_clock_propagation propagated" cmd. How much margin do we have if we use slow lib to synthesize the design?
 

Re: Synthesis lib

dannyic said:
dannyic said:
Thinkie said:
25% is quite a lot.

if your clock is 4ns (250MHz) you should have 10-15% margin plus your clock jitter. You can find the clock jitter from your pll specification if it comes from a PLL.

After PnR when you have exact clock skew information you can probably lower your margins on the final sign-off STA
Click to expand...

how do you define the clock with 10-15% margin? is it defined as 3.8 ns or 4.2 ns? please advise! Thanks.
Click to expand...

anyone can help this out.
Click to expand...

Adding margin this way you would speed up the clock, so 3.8ns for a 4ns clock would be 5% margin

Added after 10 minutes:

dannyic said:
Thinkie said:
If you use the clock_uncertainty you should not have it for hold times too as you will get a design full of buffers that you don't really need.

You can use a different value of certainty of hold and different of setup times
Click to expand...

I think set_clock_uncertainty is used during prelayout stage. For post layout, I am using "set_clock_propagation propagated" cmd. How much margin do we have if we use slow lib to synthesize the design?
Click to expand...

For postlayout you may want to use set_clock_uncertainty for some extra hold margin. Also, if you are timing a block with two clocks coming into the block that talk to each other, set uncertainty from clkA to clkB and vice versa. This accounts for their external skews.
 

Synthesis lib

hi all,

previously in my message i have explained that 25% margen(it is according to the my observations in the project and it i also the worest case) is required for the clock.but is not the exact figure the clock margen is depends on the design type,PLL char,possible clock skew,design freq and the technology.i will change it if i get the customised wireload model.

regards,.
ramesh.s
 

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